MarcioPG

Alguém poderia me ajudar a consertar alguns erros em vhdl? Meu código: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity DataP is port( clk, rst: in std_logic; entrada, din_ram: in std_logic_vector(7 downto 0); ram_wr: out std_logic; r_addr_reg, p_addr_reg: out std_logic_vector(3 downto 0); dout_ram: out std_logic_vector(7 downto 0) ); end DataP; architecture DataP_arc of FSM is signal mux, ram_wrAux: std_logic; signal r_d_reg_enA, result_enA, op1_reg_enA, op2_reg_enA, r_addr_reg_enA, p_addr_reg_enA: std_logic; signal op1, op2: std_logic_vector(7 downto 0); signal result, result_ULA: std_logic_vector(7 downto 0); signal Sig_r_addr_reg, Sig_p_addr_reg: std_logic_vector(3 downto 0); begin PFSM: entity work.FSM port map( inst => dout_rom, clk => clk, rst => rst, ram_wr => ram_wrAux, sel_ram => mux, r_d_reg_en => r_d_reg_enA, result_en => result_enA, op1_reg_en => op1_reg_enA, op2_reg_en => op2_reg_enA, r_addr_reg_en => r_addr_reg_enA, p_addr_reg_en => p_addr_reg_enA ); att_r_addr_reg:process(clk, rst, r_addr_reg_enA) begin if rst = '1' then Sig_r_addr_reg <= "0000"; elsif clk'event and clk = '1' then if r_addr_reg_enA = '1' then Sig_r_addr_reg <= Sig_r_addr_reg + "0001"; end if ; end if; r_addr_reg <= Sig_r_addr_reg; end process; operadores:process(clk, op1_reg_enA, op2_reg_enA) begin if clk'event and clk = '1' then if op1_reg_enA = '1' then op1 <= din_ram; end if; if op2_reg_enA = '1' then op2 <= din_ram; end if; end if; end process; ula:process(clk, r_d_reg_enA) begin if clk'event and clk = '1' then if r_d_reg_enA = '1' then result_ULA <=-- op1 + op2 when inst(7) = '1' and inst(2 downto 0) = "000" else --op1 - op2 when inst(7) = '1' and inst(2) = '0' and inst(1) = '0' and inst(0) = '1' else --op1 + 1 when inst(7) = '1' and inst(2) = '0' and inst(1) = '1' and inst(0) = '0' else --op1 - 1 when inst(7) = '1' and inst(2) = '0' and inst(1) = '1' and inst(0) = '1' else (op1 and op2) when inst(7) = '1' and inst(2) = '1' and inst(1) = '0' and inst(0) = '0' else (op1 or op2) when inst(7) = '1' and inst(2) = '1' and inst(1) = '0' and inst(0) = '1' else not(op1); end if; end if; end process; resultado:process(clk, result_enA) begin if clk'event and clk = '1' then if result_enA = '1' then result <= result_ULA; end if ; end if; end process; att_p_addr_reg:process(clk, p_addr_reg_enA) begin if clk'event and clk = '1' then if p_addr_reg_enA = '1' then if ram_wrAux = '0' then Sig_p_addr_reg <= Sig_p_addr_reg - 1; else Sig_p_addr_reg <= Sig_p_addr_reg + '1'; end if ; p_addr_reg <= Sig_p_addr_reg; end if ; end if; end process; dout_ram <= dout_rom when mux = '0' else result; end; E os erros são os seguintes: # ** Error: C:/Users/Usuário/Desktop/vhdl/datapath.vhd(26): (vcom-1136) Unknown identifier "dout_rom". # # ** Error: C:/Users/Usuário/Desktop/vhdl/datapath.vhd(45): No feasible entries for infix operator "+". # ** Error: C:/Users/Usuário/Desktop/vhdl/datapath.vhd(45): Type error resolving infix expression "+" as type ieee.std_logic_1164.STD_LOGIC_VECTOR. # ** Error: C:/Users/Usuário/Desktop/vhdl/datapath.vhd(48): Illegal target for signal assignment. # ** Error: C:/Users/Usuário/Desktop/vhdl/datapath.vhd(48): (vcom-1136) Unknown identifier "r_addr_reg". # # ** Error: C:/Users/Usuário/Desktop/vhdl/datapath.vhd(56): (vcom-1136) Unknown identifier "din_ram". # # ** Error: C:/Users/Usuário/Desktop/vhdl/datapath.vhd(59): (vcom-1136) Unknown identifier "din_ram". # # ** Error: C:/Users/Usuário/Desktop/vhdl/datapath.vhd(72): Illegal sequential statement. # ** Error: C:/Users/Usuário/Desktop/vhdl/datapath.vhd(73): Illegal sequential statement. # ** Error: C:/Users/Usuário/Desktop/vhdl/datapath.vhd(95): No feasible entries for infix operator "-". # ** Error: C:/Users/Usuário/Desktop/vhdl/datapath.vhd(95): Type error resolving infix expression "-" as type ieee.std_logic_1164.STD_LOGIC_VECTOR. # ** Error: C:/Users/Usuário/Desktop/vhdl/datapath.vhd(97): No feasible entries for infix operator "+". # ** Error: C:/Users/Usuário/Desktop/vhdl/datapath.vhd(97): Type error resolving infix expression "+" as type ieee.std_logic_1164.STD_LOGIC_VECTOR. # ** Error: C:/Users/Usuário/Desktop/vhdl/datapath.vhd(99): Illegal target for signal assignment. # ** Error: C:/Users/Usuário/Desktop/vhdl/datapath.vhd(99): (vcom-1136) Unknown identifier "p_addr_reg". # # ** Error: C:/Users/Usuário/Desktop/vhdl/datapath.vhd(105): Illegal target for signal assignment. # ** Error: C:/Users/Usuário/Desktop/vhdl/datapath.vhd(105): (vcom-1136) Unknown identifier "dout_ram". # # ** Error: C:/Users/Usuário/Desktop/vhdl/datapath.vhd(105): Signal "result" is type ieee.std_logic_1164.STD_LOGIC_VECTOR; expecting type (error). # ** Error: C:/Users/Usuário/Desktop/vhdl/datapath.vhd(107): VHDL Compiler exiting # End time: 11:06:50 on Nov 23,2016, Elapsed time: 0:00:00 # Errors: 19, Warnings: 0 # C:/Modeltech_pe_edu_10.4a/win32pe_edu/vcom failed. Grato desde já