[DEVICE]
FILE=M1284PDEFOK.DAT        ; file name
pdf=atmega1284p.pdf
atmelpdfurl=http://www.atmel.com/Images/doc8059.pdf
pdfurl=http://www.mcselec.com/atmelpdf/atmega1284p.pdf
device = ATMEGA1284P
UP = M1284              ; shortname for micro
RAMSTART = $100         ; start of SRAM memory
_CHIP=103            ; FOr backwards compatibility
RAMEND  =$40FF	;Last On-Chip SRAM location
XRAMEND =$40FF
E2END	=$FFF
FLASHEND=$FFFF
FlashSizeText = 128 KB
SRAM = 16384           ; SRAM size
EEPROM = 4096           ; EEPROM size
XRAMINDEX = 0           ; default no XRAM selected
XRAM = 0                ; do not allow XRAM
WAITSTATE=0             ; no wait state
WAITSTATEENABLE=0       ; disable setting the wait state
XRAMACCESS=0            ; no external memory access selected
XRAMACESSENABLE=0       ; external memory access can not be selected
UBRR = 4096             ; calculation of baudrate
TINY= 0                  ; no tiny micro without sram
HWMUL=1                 ; this chip has hardware multiplication
MOVW=1                  ; micro has movw instruction
ROMSIZE = 131072         ; size of rom in bytes
SPI_CLock=B,7           ; HW SPI clock pin
SPI_MISO=B,6            ; HW SPI MISO pin
SPI_MOSI= B,5           ; HW SPI MOSI pin
SPI_SS=B,4              ; HW SPI SS pin
INTADR = 2              ; multiple of 2 words
MEGAJMP=1                  ; Mega part
MEGAPROG=1              ; program with pages method
MEGAPAGE=7             ; number of pages
PROGWAITMS=0            ; delay for programming
WRAP=0                  ; no address wrap
DEVID=1E9705            ; device ID

JTD=MCUCR.7
IVSEL=MCUCR,IVCE,IVSEL
AIN0_PORT=PORTB         ; analog comparator port
AIN0_PIN=2              ; analog comparator pin
T0_PULSE=PORTB.0        ; pulse generator TIMER 0
T1_PULSE=PORTB.1        ; pulse generator TIMER 1
OCR1A_PORT=PORTD.5      ; Output compare TIMER1A
INT=$5B,64, $5A,64 , $5B,128, $5A,128 ,  $5B,32 , $5A,32, $59,128, $58,128 , $59,64, $58,64, $59,32, $58,32, $59,16, $58,16 , $59,8, $58,8 , $59,4, $58,4 , $59,2, $58,2, $59,1, $58,1, $2D,128,$2E,128, $2A,128,$2B,128 , $2A,32,$2B,32, $2A,64,$2B,64, $26,8,$26,16 ,  $3C,8,0,0  , $28,8,$28,16, $56,1,$56,128
ADFR=160                 ; AD converter free running mode
ADC_REFMODEL=5          ; AD converter  reference
ADC_MUX=5,ADMUX.0-4
CheckSBIC=0             ; do not check SBIC with JMP CALL
SCL=PORTC.0
SDA=PORTC.1
uarts=2
uart1=5
uart2=5
avr910_devcode=0

ints=3                    ; ext ints
int1=INT0,EIMSK.0,4       ; intname, enable register and bit, number of modes
int1m1=LOW LEVEL,EICRA.0-0,EICRA.1-0    ;first mode, bits to set and value
int1m2=CHANGE,EICRA.0-1,EICRA.1-0
int1m3=FALLING,EICRA.0-0,EICRA.1-1
int1m4=RISING,EICRA.0-1,EICRA.1-1
int2=INT1,EIMSK.1,4       ; intname, enable register and bit, number of modes
int2m1=LOW LEVEL,EICRA.2-0,EICRA.3-0    ;first mode, bits to set and value
int2m2=CHANGE,EICRA.2-1,EICRA.3-0
int2m3=FALLING,EICRA.2-0,EICRA.3-1
int2m4=RISING,EICRA.2-1,EICRA.3-1
int3=INT2,EIMSK.2,4       ; intname, enable register and bit, number of modes
int3m1=LOW LEVEL,EICRA.4-0,EICRA.5-0    ;first mode, bits to set and value
int3m2=CHANGE,EICRA.4-1,EICRA.5-0
int3m3=FALLING,EICRA.4-0,EICRA.5-1
int3m4=RISING,EICRA.4-1,EICRA.5-1
WD=MCUSR.WDRF
NEWPORT=1

Powermodes=6
SE=SMCR.0
Pm1=Idle,SMCR.SM0-0,SMCR.SM1-0,SMCR.SM2-0
Pm2=Powerdown,SMCR.SM0-0,SMCR.SM1-1,SMCR.SM2-0
Pm3=Standby,SMCR.SM0-0,SMCR.SM1-1,SMCR.SM2-1
Pm4=ADCnoise,SMCR.SM0-1,SMCR.SM1-0,SMCR.SM2-0
Pm5=Powersave,SMCR.SM0-1,SMCR.SM1-1,SMCR.SM2-0
Pm6=ExStandby,SMCR.SM0-1,SMCR.SM1-1,SMCR.SM2-1

WDVALUE=16,32,64,128,256,512,1024,2048,4096,8192
ICP1=PORTD.6,1@8@64@256@1024

[PROG]
chipname=MEGA1284P

readLB=3,58,00,FF,xx,65,43,21
writeLB=3,AC,FF,FF,xx,65,43,21

21-11=No memory lock features enabled for parallel and serial programming
21-10=Further programming of the flash and eprom is disabled in parallel and serial programming mode. The fuse bits are locked in both serial and parallel mode
21-00=Further programming and verification of the flash and eeprom is disabled in parallel and serial programming mode. The fuse bits are locked in both serial and parallel programming mode

43-11=No restrictions for SPM or LPM accessing the application section
43-10=SPM is not allowed to write to the application section
43-00=SPM is not allowed to write to the application section. Interupt vectors are placed in the boot loader section, ints are disabled while executing from the app section
43-01=LPM executing from the boot loader section is not allowed to read from the appliation section. If interrupts vectors are placed in the boot loader section interrupts are disabled while executing from the application section

65-11=No restrictions for SPM or LPM accessing the boot loader section
65-10=SPM is not allowed to write to the boot loader section
65-00=SPM is not allowed to write to the boot loader section and LPM executing from the application section is not allowed to read from the boot loader section. If int vectors are placed in the application section, ints are disabled while executing from the boot loader section
65-01=LPM executing from the application section is not allowed to read from the boot loader section. If int vectors are placed in the app section, ints are disabled while executing from the boot loader section

readFS=3,50,00,FF,C,B,KLA987
writeFS=3,AC,A0,FF,C,B,KLA987
KLA987-000000=Ext. Clock; Start-up time: 6 CK + 0 ms
KLA987-010000=Ext. Clock; Start-up time: 6 CK + 4.1 ms
KLA987-100000=Ext. Clock; Start-up time: 6 CK + 65 ms
KLA987-000010=Int. RC Osc.; Start-up time: 6 CK + 0 ms
KLA987-010010=Int. RC Osc.; Start-up time: 6 CK + 4.1 ms
KLA987-100010=Int. RC Osc.; Start-up time: 6 CK + 65 ms
KLA987-000011=Int. 128kHz RC Osc.; Start-up time: 6 CK + 0 ms
KLA987-010011=Int. 128kHz RC Osc.; Start-up time: 6 CK + 4 ms
KLA987-100011=Int. 128kHz RC Osc.; Start-up time: 6 CK + 64 ms
KLA987-000100=Ext. Low-Freq. Crystal; Start-up time: 1K CK + 0 ms
KLA987-010100=Ext. Low-Freq. Crystal; Start-up time: 1K CK + 4.1 ms
KLA987-100100=Ext. Low-Freq. Crystal; Start-up time: 1K CK + 65 ms
KLA987-000101=Ext. Low-Freq. Crystal; Start-up time: 32K CK + 0 ms
KLA987-010101=Ext. Low-Freq. Crystal; Start-up time: 32K CK + 4.1 ms
KLA987-100101=Ext. Low-Freq. Crystal; Start-up time: 32K CK + 65 ms
KLA987-000110=Full Swing Oscillator; Start-up time: 258 CK + 4.1 ms; Ceramic res.; fast rising power
KLA987-010110=Full Swing Oscillator; Start-up time: 258 CK + 65 ms; Ceramic res.; slowly rising power
KLA987-100110=Full Swing Oscillator; Start-up time: 1K CK + 0 ms; Ceramic res.; BOD enable
KLA987-110110=Full Swing Oscillator; Start-up time: 1K CK + 4.1 ms; Ceramic res.; fast rising power
KLA987-000111=Full Swing Oscillator; Start-up time: 1K CK + 65 ms; Ceramic res.; slowly rising power
KLA987-010111=Full Swing Oscillator; Start-up time: 16K CK + 0 ms; Crystal Osc.; BOD enabled
KLA987-100111=Full Swing Oscillator; Start-up time: 16K CK + 4.1 ms; Crystal Osc.; fast rising power
KLA987-110111=Full Swing Oscillator; Start-up time: 16K CK + 65 ms; Crystal Osc.; slowly rising power
KLA987-001000=Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 258 CK + 4.1 ms
KLA987-011000=Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 258 CK + 65 ms;
KLA987-101000=Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 1K CK + 0 ms
KLA987-111000=Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 1K CK + 4.1 ms;
KLA987-001001=Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 1K CK + 65 ms
KLA987-011001=Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 16K CK + 0 ms
KLA987-101001=Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 16K CK + 4.1 ms
KLA987-111001=Ext. Crystal Osc.; Frequency 0.4-0.9 MHz; Start-up time: 16K CK + 65 ms
KLA987-001010=Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 258 CK + 4.1 ms
KLA987-011010=Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 258 CK + 65 ms
KLA987-101010=Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 1K CK + 0 ms
KLA987-111010=Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 1K CK + 4.1 ms
KLA987-001011=Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 1K CK + 65 ms
KLA987-011011=Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 16K CK + 0 ms;
KLA987-101011=Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 16K CK + 4.1 ms
KLA987-111011=Ext. Crystal Osc.; Frequency 0.9-3.0 MHz; Start-up time: 16K CK + 65 ms
KLA987-001100=Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 258 CK + 4.1 ms
KLA987-011100=Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 258 CK + 65 ms
KLA987-101100=Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 1K CK + 0 ms
KLA987-111100=Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 1K CK + 4.1 ms
KLA987-001101=Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 1K CK + 65 ms
KLA987-011101=Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 16K CK + 0 ms
KLA987-101101=Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 16K CK + 4.1 ms
KLA987-111101=Ext. Crystal Osc.; Frequency 3.0-8.0 MHz; Start-up time: 16K CK + 65 ms
KLA987-001110=Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 258 CK + 4.1 ms
KLA987-011110=Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 258 CK + 65 ms
KLA987-101110=Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 1K CK + 0 ms
KLA987-111110=Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 1K CK + 4.1 ms
KLA987-001111=Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 1K CK + 65 ms
KLA987-011111=Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 16K CK + 0 ms
KLA987-101111=Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 16K CK + 4.1 ms
KLA987-111111=Ext. Crystal Osc.; Frequency 8.0- MHz; Start-up time: 16K CK + 65 ms
KLA987-000001=reserved
KLA987-010001=reserved
KLA987-100001=reserved
KLA987-110000=reserved
KLA987-110001=reserved
KLA987-110010=reserved
KLA987-110011=reserved
KLA987-110100=reserved
KLA987-110101=reserved
C-0=Divison by 8 enabled
C-1=Division by 8 disabled
B-0=Clock output enabled
B-1=Clock output disabled



readFSH=3,58,08,00,I,H,Q,P,G,FE,D
writeFSH=3,AC,A8,00,I,H,Q,P,G,FE,D
D-0=Reset vector is boot loader reset
D-1=Reset vector is $0000
FE-11=512 Words boot size
FE-10=1024 words boot size
FE-01=2048 words boot size
FE-00=4096 words boot size
G-0=Preserve EEPROM when chip erase
G-1=Erase EEPROM when chip erase
P-0=Watchdog timer always on ENABLED
P-1=Watchdog timer always on DISABLED
I-0=OCDEN fuse programmed
I-1=OCDEN fuse unprogrammed
H-0=JTAG enabled(portc.2-portc.5 not usable)
H-1=JTAG disabled
Q-0=Serial programming enabled
Q-1=Serial programming disabled

readFSE=3,50,08,00,xxxxx,TSR
writeFSE=3,AC,A4,00,xxxxx,TSR
TSR-000=reserved
TSR-001=reserved
TSR-010=reserved
TSR-011=reserved
TSR-100=Brown-out detection level at VCC=4.3 V
TSR-101=Brown-out detection level at VCC=2.7 V
TSR-110=Brown-out detection level at VCC=1.8 V
TSR-111=Brown-out disabled





readcalibration=3,38,FF,00

[IOEXT]
UDR1  =$ce	; MEMORY MAPPED
UBRR1L=$cc	; MEMORY MAPPED
UBRR1H=$cd	; MEMORY MAPPED
UCSR1C=$ca	; MEMORY MAPPED
UCSR1B=$c9	; MEMORY MAPPED
UCSR1A=$c8	; MEMORY MAPPED
USR1=$C8
UDR0=$C6
UDR=$C6
UBRR0L	= $c4	; MEMORY MAPPED
UBRR=$C4
UBRRL=$C4
UBRR0H	= $c5	; MEMORY MAPPED
UBRRHI=$C5
UCSRC=$C2 ; remove
UCSR0C	= $c2	; MEMORY MAPPED
UCSR0B	= $c1	; MEMORY MAPPED
UCR=$C1
UCSR0A	= $c0	; MEMORY MAPPED
USR=$C0
TWAMR	= $bd	; MEMORY MAPPED
TWCR	= $bc	; MEMORY MAPPED
TWDR	= $bb	; MEMORY MAPPED
TWAR	= $ba	; MEMORY MAPPED
TWSR	= $b9	; MEMORY MAPPED
TWBR	= $b8	; MEMORY MAPPED
ASSR	= $b6	; MEMORY MAPPED
OCR2B	= $b4	; MEMORY MAPPED
PWM2B= $b4	; MEMORY MAPPED
COMPARE2B= $b4	; MEMORY MAPPED
OCR2A	= $b3	; MEMORY MAPPED
COMPARE2A= $b3	; MEMORY MAPPED
PWM2A= $b3	; MEMORY MAPPED
TCNT2	= $b2	; MEMORY MAPPED
TIMER2= $b2	; MEMORY MAPPED
COUNTER2= $b2	; MEMORY MAPPED
TCCR2B	= $b1	; MEMORY MAPPED
TCCR2=$B1
TCCR2A= $b0	; MEMORY MAPPED
OCR3BL=$9a	; MEMORY MAPPED
OCR3BH=$9b	; MEMORY MAPPED
OCR3AL=$98	; MEMORY MAPPED
OCR3AH=$99	; MEMORY MAPPED
ICR3L=$96	; MEMORY MAPPED
ICR3H=$97	; MEMORY MAPPED
TCNT3L=$94	; MEMORY MAPPED
TCNT3H=$95	; MEMORY MAPPED
TCCR3C=$92	; MEMORY MAPPED
TCCR3B=$91	; MEMORY MAPPED
TCCR3A=$90	; MEMORY MAPPED
OCR1BL	= $8a	; MEMORY MAPPED
OCR1BH	= $8b	; MEMORY MAPPED
OCR1AL	= $88	; MEMORY MAPPED
OCR1AH	= $89	; MEMORY MAPPED
ICR1L	= $86	; MEMORY MAPPED
ICR1H	= $87	; MEMORY MAPPED
TCNT1L	= $84	; MEMORY MAPPED
TCNT1H	= $85	; MEMORY MAPPED
TCCR1C	= $82	; MEMORY MAPPED
TCCR1B	= $81	; MEMORY MAPPED
TCCR1A	= $80	; MEMORY MAPPED
DIDR1	= $7f	; MEMORY MAPPED
DIDR0	= $7e	; MEMORY MAPPED
ADMUX	= $7c	; MEMORY MAPPED
ADCSRB	= $7b	; MEMORY MAPPED
ADCSRA	= $7a	; MEMORY MAPPED
ADCSR	= $7a	; MEMORY MAPPED
ADCH	= $79	; MEMORY MAPPED
ADCL	= $78	; MEMORY MAPPED
PCMSK3	= $73	; MEMORY MAPPED
TIMSK3	= $71	; MEMORY MAPPED
TIMSK2	= $70	; MEMORY MAPPED
TIMSK1	= $6f	; MEMORY MAPPED
TIMSK0	= $6e	; MEMORY MAPPED
TIMSK	= $6e	; MEMORY MAPPED
PCMSK2	= $6d	; MEMORY MAPPED
PCMSK1	= $6c	; MEMORY MAPPED
PCMSK0	= $6b	; MEMORY MAPPED
EICRA	= $69	; MEMORY MAPPED
PCICR	= $68	; MEMORY MAPPED
OSCCAL	= $66	; MEMORY MAPPED
PRR0	= $64	; MEMORY MAPPED
CLKPR	= $61	; MEMORY MAPPED
WDTCSR	= $60	; MEMORY MAPPED
WDTCR=$60


[IO]
SREG	= $3f
SPL	= $3d
SPH	= $3e
RAMPZ	= $3b
SPMCSR	= $37
MCUCR	= $35
MCUSR	= $34
MCUCSR=$34
SMCR	= $33
OCDR	= $31
ACSR	= $30
SPDR0	= $2e
SPDR = $2E
SPSR0	= $2d
SPSR=$2D
SPCR0	= $2c
SPCR=$2C
GPIOR2	= $2b
GPIOR1	= $2a
OCR0B	= $28
PWM0B= $28
COMPARE0B= $28
OCR0A	= $27
PWM0A= $27
COMPARE0A= $27
TCNT0	= $26
COUNTER0= $26
TIMER0= $26
TCCR0B	= $25
TCCR0	= $25
TCCR0A	= $24

GTCCR	= $23
EEARH	= $22
EEARL	= $21
EEDR	= $20
EECR	= $1f
GPIOR0	= $1e
EIMSK	= $1d
EIFR	= $1c
PCIFR	= $1b
TIFR3   = $18
TIFR2	= $17
TIFR1	= $16
TIFR0	= $15
PORTD	= $0b
DDRD	= $0a
PIND	= $09
PORTC	= $08
DDRC	= $07
PINC	= $06
PORTB	= $05
DDRB	= $04
PINB	= $03
PORTA	= $02
DDRA	= $01
PINA	= $00

[TIMER]
COMPARE=8

COMPARE1=COMPARE0A,PORTB.3
COMPARE2=COMPARE0B,PORTB.4

COMPARE3=COMPARE3A,PORTB.6
COMPARE4=COMPARE3B,PORTB.7

COMPARE5=COMPARE1B,PORTD.4
COMPARE6=COMPARE1A,PORTD.5

COMPARE7=COMPARE2B,PORTD.6
COMPARE8=COMPARE2A,PORTD.7



[FLAG]
EIFR
PCIFR
TIFR3
TIFR2
TIFR1
TIFR0

[CONST]
_ROMSIZE = 131072
; ***** BIT DEFINITIONS **************************************************

; ***** ANALOG_COMPARATOR ************
; ADCSRB - ADC Control and Status Register B
ACME	= 6	; Analog Comparator Multiplexer Enable

; ACSR - Analog Comparator Control And Status Register
ACIS0	= 0	; Analog Comparator Interrupt Mode Select bit 0
ACIS1	= 1	; Analog Comparator Interrupt Mode Select bit 1
ACIC	= 2	; Analog Comparator Input Capture Enable
ACIE	= 3	; Analog Comparator Interrupt Enable
ACI	= 4	; Analog Comparator Interrupt Flag
ACO	= 5	; Analog Compare Output
ACBG	= 6	; Analog Comparator Bandgap Select
ACD	= 7	; Analog Comparator Disable

; DIDR1 - Digital Input Disable Register 1
AIN0D	= 0	; AIN0 Digital Input Disable
AIN1D	= 1	; AIN1 Digital Input Disable


; ***** USART0 ***********************
; UDR0 - USART I/O Data Register
UDR0_0	= 0	; USART I/O Data Register bit 0
UDR0_1	= 1	; USART I/O Data Register bit 1
UDR0_2	= 2	; USART I/O Data Register bit 2
UDR0_3	= 3	; USART I/O Data Register bit 3
UDR0_4	= 4	; USART I/O Data Register bit 4
UDR0_5	= 5	; USART I/O Data Register bit 5
UDR0_6	= 6	; USART I/O Data Register bit 6
UDR0_7	= 7	; USART I/O Data Register bit 7

; UCSR0A - USART Control and Status Register A
MPCM0	= 0	; Multi-processor Communication Mode
U2X0	= 1	; Double the USART transmission speed
U2X	= 1
UPE0	= 2	; Parity Error
DOR0	= 3	; Data overRun
FE0	= 4	; Framing Error
UDRE0	= 5	; USART Data Register Empty
TXC0	= 6	; USART Transmitt Complete
RXC0	= 7	; USART Receive Complete

; UCSR0B - USART Control and Status Register B
TXB80	= 0	; Transmit Data Bit 8
RXB80	= 1	; Receive Data Bit 8
UCSZ02	= 2	; Character Size
TXEN0	= 3	; Transmitter Enable
RXEN0	= 4	; Receiver Enable
UDRIE0	= 5	; USART Data register Empty Interrupt Enable
TXCIE0	= 6	; TX Complete Interrupt Enable
RXCIE0	= 7	; RX Complete Interrupt Enable

; UCSR0C - USART Control and Status Register C
UCPOL0	= 0	; Clock Polarity
UCSZ00	= 1	; Character Size
UCPHA0	= UCSZ00	; For compatibility
UCSZ01	= 2	; Character Size
UDORD0	= UCSZ01	; For compatibility
USBS0	= 3	; Stop Bit Select
UPM00	= 4	; Parity Mode Bit 0
UPM01	= 5	; Parity Mode Bit 1
UMSEL00	= 6	; USART Mode Select
UMSEL0	= UMSEL00	; For compatibility
UMSEL01	= 7	; USART Mode Select
UMSEL1	= UMSEL01	; For compatibility



; UCSR1A - USART Control and Status Register A
MPCM1	= 0	; Multi-processor Communication Mode
U2X1	= 1	; Double the USART transmission speed
UPE1	= 2	; Parity Error
DOR1	= 3	; Data overRun
FE1	= 4	; Framing Error
UDRE1	= 5	; USART Data Register Empty
TXC1	= 6	; USART Transmitt Complete
RXC1	= 7	; USART Receive Complete

; UCSR1B - USART Control and Status Register B
TXB81	= 0	; Transmit Data Bit 8
RXB81	= 1	; Receive Data Bit 8
UCSZ12	= 2	; Character Size
TXEN1	= 3	; Transmitter Enable
RXEN1	= 4	; Receiver Enable
UDRIE1	= 5	; USART Data register Empty Interrupt Enable
TXCIE1	= 6	; TX Complete Interrupt Enable
RXCIE1	= 7	; RX Complete Interrupt Enable

; UCSR1C - USART Control and Status Register C
UCPOL1	= 0	; Clock Polarity
UCSZ10	= 1	; Character Size
UCSZ11	= 2	; Character Size
USBS1	= 3	; Stop Bit Select
UPM10	= 4	; Parity Mode Bit 0
UPM11	= 5	; Parity Mode Bit 1
UMSEL10	= 6	; USART Mode Select
UMSEL11	= 7	; USART Mode Select


; ***** PORTA ************************
; PORTA - Port A Data Register
PORTA0	= 0	; Port A Data Register bit 0
PA0	= 0	; For compatibility
PORTA1	= 1	; Port A Data Register bit 1
PA1	= 1	; For compatibility
PORTA2	= 2	; Port A Data Register bit 2
PA2	= 2	; For compatibility
PORTA3	= 3	; Port A Data Register bit 3
PA3	= 3	; For compatibility
PORTA4	= 4	; Port A Data Register bit 4
PA4	= 4	; For compatibility
PORTA5	= 5	; Port A Data Register bit 5
PA5	= 5	; For compatibility
PORTA6	= 6	; Port A Data Register bit 6
PA6	= 6	; For compatibility
PORTA7	= 7	; Port A Data Register bit 7
PA7	= 7	; For compatibility

; DDRA - Port A Data Direction Register
DDA0	= 0	; Data Direction Register, Port A, bit 0
DDA1	= 1	; Data Direction Register, Port A, bit 1
DDA2	= 2	; Data Direction Register, Port A, bit 2
DDA3	= 3	; Data Direction Register, Port A, bit 3
DDA4	= 4	; Data Direction Register, Port A, bit 4
DDA5	= 5	; Data Direction Register, Port A, bit 5
DDA6	= 6	; Data Direction Register, Port A, bit 6
DDA7	= 7	; Data Direction Register, Port A, bit 7

; PINA - Port A Input Pins
PINA0	= 0	; Input Pins, Port A bit 0
PINA1	= 1	; Input Pins, Port A bit 1
PINA2	= 2	; Input Pins, Port A bit 2
PINA3	= 3	; Input Pins, Port A bit 3
PINA4	= 4	; Input Pins, Port A bit 4
PINA5	= 5	; Input Pins, Port A bit 5
PINA6	= 6	; Input Pins, Port A bit 6
PINA7	= 7	; Input Pins, Port A bit 7


; ***** PORTB ************************
; PORTB - Port B Data Register
PORTB0	= 0	; Port B Data Register bit 0
PB0	= 0	; For compatibility
PORTB1	= 1	; Port B Data Register bit 1
PB1	= 1	; For compatibility
PORTB2	= 2	; Port B Data Register bit 2
PB2	= 2	; For compatibility
PORTB3	= 3	; Port B Data Register bit 3
PB3	= 3	; For compatibility
PORTB4	= 4	; Port B Data Register bit 4
PB4	= 4	; For compatibility
PORTB5	= 5	; Port B Data Register bit 5
PB5	= 5	; For compatibility
PORTB6	= 6	; Port B Data Register bit 6
PB6	= 6	; For compatibility
PORTB7	= 7	; Port B Data Register bit 7
PB7	= 7	; For compatibility

; DDRB - Port B Data Direction Register
DDB0	= 0	; Port B Data Direction Register bit 0
DDB1	= 1	; Port B Data Direction Register bit 1
DDB2	= 2	; Port B Data Direction Register bit 2
DDB3	= 3	; Port B Data Direction Register bit 3
DDB4	= 4	; Port B Data Direction Register bit 4
DDB5	= 5	; Port B Data Direction Register bit 5
DDB6	= 6	; Port B Data Direction Register bit 6
DDB7	= 7	; Port B Data Direction Register bit 7

; PINB - Port B Input Pins
PINB0	= 0	; Port B Input Pins bit 0
PINB1	= 1	; Port B Input Pins bit 1
PINB2	= 2	; Port B Input Pins bit 2
PINB3	= 3	; Port B Input Pins bit 3
PINB4	= 4	; Port B Input Pins bit 4
PINB5	= 5	; Port B Input Pins bit 5
PINB6	= 6	; Port B Input Pins bit 6
PINB7	= 7	; Port B Input Pins bit 7


; ***** PORTC ************************
; PORTC - Port C Data Register
PORTC0	= 0	; Port C Data Register bit 0
PC0	= 0	; For compatibility
PORTC1	= 1	; Port C Data Register bit 1
PC1	= 1	; For compatibility
PORTC2	= 2	; Port C Data Register bit 2
PC2	= 2	; For compatibility
PORTC3	= 3	; Port C Data Register bit 3
PC3	= 3	; For compatibility
PORTC4	= 4	; Port C Data Register bit 4
PC4	= 4	; For compatibility
PORTC5	= 5	; Port C Data Register bit 5
PC5	= 5	; For compatibility
PORTC6	= 6	; Port C Data Register bit 6
PC6	= 6	; For compatibility
PORTC7	= 7	; Port C Data Register bit 7
PC7	= 7	; For compatibility

; DDRC - Port C Data Direction Register
DDC0	= 0	; Port C Data Direction Register bit 0
DDC1	= 1	; Port C Data Direction Register bit 1
DDC2	= 2	; Port C Data Direction Register bit 2
DDC3	= 3	; Port C Data Direction Register bit 3
DDC4	= 4	; Port C Data Direction Register bit 4
DDC5	= 5	; Port C Data Direction Register bit 5
DDC6	= 6	; Port C Data Direction Register bit 6
DDC7	= 7	; Port C Data Direction Register bit 7

; PINC - Port C Input Pins
PINC0	= 0	; Port C Input Pins bit 0
PINC1	= 1	; Port C Input Pins bit 1
PINC2	= 2	; Port C Input Pins bit 2
PINC3	= 3	; Port C Input Pins bit 3
PINC4	= 4	; Port C Input Pins bit 4
PINC5	= 5	; Port C Input Pins bit 5
PINC6	= 6	; Port C Input Pins bit 6
PINC7	= 7	; Port C Input Pins bit 7


; ***** PORTD ************************
; PORTD - Port D Data Register
PORTD0	= 0	; Port D Data Register bit 0
PD0	= 0	; For compatibility
PORTD1	= 1	; Port D Data Register bit 1
PD1	= 1	; For compatibility
PORTD2	= 2	; Port D Data Register bit 2
PD2	= 2	; For compatibility
PORTD3	= 3	; Port D Data Register bit 3
PD3	= 3	; For compatibility
PORTD4	= 4	; Port D Data Register bit 4
PD4	= 4	; For compatibility
PORTD5	= 5	; Port D Data Register bit 5
PD5	= 5	; For compatibility
PORTD6	= 6	; Port D Data Register bit 6
PD6	= 6	; For compatibility
PORTD7	= 7	; Port D Data Register bit 7
PD7	= 7	; For compatibility

; DDRD - Port D Data Direction Register
DDD0	= 0	; Port D Data Direction Register bit 0
DDD1	= 1	; Port D Data Direction Register bit 1
DDD2	= 2	; Port D Data Direction Register bit 2
DDD3	= 3	; Port D Data Direction Register bit 3
DDD4	= 4	; Port D Data Direction Register bit 4
DDD5	= 5	; Port D Data Direction Register bit 5
DDD6	= 6	; Port D Data Direction Register bit 6
DDD7	= 7	; Port D Data Direction Register bit 7

; PIND - Port D Input Pins
PIND0	= 0	; Port D Input Pins bit 0
PIND1	= 1	; Port D Input Pins bit 1
PIND2	= 2	; Port D Input Pins bit 2
PIND3	= 3	; Port D Input Pins bit 3
PIND4	= 4	; Port D Input Pins bit 4
PIND5	= 5	; Port D Input Pins bit 5
PIND6	= 6	; Port D Input Pins bit 6
PIND7	= 7	; Port D Input Pins bit 7


; ***** TIMER_COUNTER_0 **************
; TIMSK0 - Timer/Counter0 Interrupt Mask Register
TOIE0	= 0	; Timer/Counter0 Overflow Interrupt Enable
OCIE0A	= 1	; Timer/Counter0 Output Compare Match A Interrupt Enable
OCIE0B	= 2	; Timer/Counter0 Output Compare Match B Interrupt Enable

; TIFR0 - Timer/Counter0 Interrupt Flag register
TOV0	= 0	; Timer/Counter0 Overflow Flag
OCF0A	= 1	; Timer/Counter0 Output Compare Flag 0A
OCF0B	= 2	; Timer/Counter0 Output Compare Flag 0B

; TCCR0A - Timer/Counter  Control Register A
WGM00	= 0	; Waveform Generation Mode
WGM01	= 1	; Waveform Generation Mode
COM0B0	= 4	; Compare Output Mode, Fast PWm
COM0B1	= 5	; Compare Output Mode, Fast PWm
COM0A0	= 6	; Compare Output Mode, Phase Correct PWM Mode
COM0A1	= 7	; Compare Output Mode, Phase Correct PWM Mode

; TCCR0B - Timer/Counter Control Register B
CS00	= 0	; Clock Select
CS01	= 1	; Clock Select
CS02	= 2	; Clock Select
WGM02	= 3	;
FOC0B	= 6	; Force Output Compare B
FOC0A	= 7	; Force Output Compare A

; TCNT0 - Timer/Counter0
TCNT0_0	= 0	;
TCNT0_1	= 1	;
TCNT0_2	= 2	;
TCNT0_3	= 3	;
TCNT0_4	= 4	;
TCNT0_5	= 5	;
TCNT0_6	= 6	;
TCNT0_7	= 7	;

; OCR0A - Timer/Counter0 Output Compare Register
OCR0A_0	= 0	;
OCR0A_1	= 1	;
OCR0A_2	= 2	;
OCR0A_3	= 3	;
OCR0A_4	= 4	;
OCR0A_5	= 5	;
OCR0A_6	= 6	;
OCR0A_7	= 7	;

; OCR0B - Timer/Counter0 Output Compare Register
OCR0B_0	= 0	;
OCR0B_1	= 1	;
OCR0B_2	= 2	;
OCR0B_3	= 3	;
OCR0B_4	= 4	;
OCR0B_5	= 5	;
OCR0B_6	= 6	;
OCR0B_7	= 7	;

; GTCCR - General Timer/Counter Control Register
PSRSYNC	= 0	; Prescaler Reset Timer/Counter1 and Timer/Counter0
PSR10	= PSRSYNC	; For compatibility
TSM	= 7	; Timer/Counter Synchronization Mode


; ***** TIMER_COUNTER_2 **************
; TIMSK2 - Timer/Counter Interrupt Mask register
TOIE2	= 0	; Timer/Counter2 Overflow Interrupt Enable
TOIE2A	= TOIE2	; For compatibility
OCIE2A	= 1	; Timer/Counter2 Output Compare Match A Interrupt Enable
OCIE2B	= 2	; Timer/Counter2 Output Compare Match B Interrupt Enable

; TIFR2 - Timer/Counter Interrupt Flag Register
TOV2	= 0	; Timer/Counter2 Overflow Flag
OCF2A	= 1	; Output Compare Flag 2A
OCF2B	= 2	; Output Compare Flag 2B

; TCCR2A - Timer/Counter2 Control Register A
WGM20	= 0	; Waveform Genration Mode
WGM21	= 1	; Waveform Genration Mode
COM2B0	= 4	; Compare Output Mode bit 0
COM2B1	= 5	; Compare Output Mode bit 1
COM2A0	= 6	; Compare Output Mode bit 1
COM2A1	= 7	; Compare Output Mode bit 1

; TCCR2B - Timer/Counter2 Control Register B
CS20	= 0	; Clock Select bit 0
CS21	= 1	; Clock Select bit 1
CS22	= 2	; Clock Select bit 2
WGM22	= 3	; Waveform Generation Mode
FOC2B	= 6	; Force Output Compare B
FOC2A	= 7	; Force Output Compare A

; TCNT2 - Timer/Counter2
TCNT2_0	= 0	; Timer/Counter 2 bit 0
TCNT2_1	= 1	; Timer/Counter 2 bit 1
TCNT2_2	= 2	; Timer/Counter 2 bit 2
TCNT2_3	= 3	; Timer/Counter 2 bit 3
TCNT2_4	= 4	; Timer/Counter 2 bit 4
TCNT2_5	= 5	; Timer/Counter 2 bit 5
TCNT2_6	= 6	; Timer/Counter 2 bit 6
TCNT2_7	= 7	; Timer/Counter 2 bit 7

; OCR2A - Timer/Counter2 Output Compare Register A
OCR2_0	= 0	; Timer/Counter2 Output Compare Register Bit 0
OCR2_1	= 1	; Timer/Counter2 Output Compare Register Bit 1
OCR2_2	= 2	; Timer/Counter2 Output Compare Register Bit 2
OCR2_3	= 3	; Timer/Counter2 Output Compare Register Bit 3
OCR2_4	= 4	; Timer/Counter2 Output Compare Register Bit 4
OCR2_5	= 5	; Timer/Counter2 Output Compare Register Bit 5
OCR2_6	= 6	; Timer/Counter2 Output Compare Register Bit 6
OCR2_7	= 7	; Timer/Counter2 Output Compare Register Bit 7

; OCR2B - Timer/Counter2 Output Compare Register B
;.equ	OCR2_0	= 0	; Timer/Counter2 Output Compare Register Bit 0
;.equ	OCR2_1	= 1	; Timer/Counter2 Output Compare Register Bit 1
;.equ	OCR2_2	= 2	; Timer/Counter2 Output Compare Register Bit 2
;.equ	OCR2_3	= 3	; Timer/Counter2 Output Compare Register Bit 3
;.equ	OCR2_4	= 4	; Timer/Counter2 Output Compare Register Bit 4
;.equ	OCR2_5	= 5	; Timer/Counter2 Output Compare Register Bit 5
;.equ	OCR2_6	= 6	; Timer/Counter2 Output Compare Register Bit 6
;.equ	OCR2_7	= 7	; Timer/Counter2 Output Compare Register Bit 7

; ASSR - Asynchronous Status Register
TCR2BUB	= 0	; Timer/Counter Control Register2 Update Busy
TCR2AUB	= 1	; Timer/Counter Control Register2 Update Busy
OCR2BUB	= 2	; Output Compare Register 2 Update Busy
OCR2AUB	= 3	; Output Compare Register2 Update Busy
TCN2UB	= 4	; Timer/Counter2 Update Busy
AS2	= 5	; Asynchronous Timer/Counter2
EXCLK	= 6	; Enable External Clock Input

; GTCCR - General Timer Counter Control register
PSRASY	= 1	; Prescaler Reset Timer/Counter2
PSR2	= PSRASY	; For compatibility
;.equ	TSM	= 7	; Timer/Counter Synchronization Mode

; ***** TIMER_COUNTER_3 **************
; TIMSK3 - Timer/Counter3 Interrupt Mask Register
TOIE3	= 0	; Timer/Counter3 Overflow Interrupt Enable
OCIE3A	= 1	; Timer/Counter3 Output Compare A Match Interrupt Enable
OCIE3B	= 2	; Timer/Counter3 Output Compare B Match Interrupt Enable
ICIE3	= 5	; Timer/Counter3 Input Capture Interrupt Enable

; TIFR3 - Timer/Counter Interrupt Flag register
TOV3	= 0	; Timer/Counter3 Overflow Flag
OCF3A	= 1	; Timer/Counter3 Output Compare A Match Flag
OCF3B	= 2	; Timer/Counter3 Output Compare B Match Flag
ICF3	= 5	; Timer/Counter3 Input Capture Flag

; TCCR3A - Timer/Counter3 Control Register A
WGM30	= 0	; Pulse Width Modulator Select Bit 0
WGM31	= 1	; Pulse Width Modulator Select Bit 1
COM3B0	= 4	; Comparet Ouput Mode 3B, bit 0
COM3B1	= 5	; Compare Output Mode 3B, bit 1
COM3A0	= 6	; Comparet Ouput Mode 3A, bit 0
COM3A1	= 7	; Compare Output Mode 3A, bit 1

; TCCR3B - Timer/Counter3 Control Register B
CS30	= 0	; Clock Select bit 0
CS31	= 1	; Clock Select 3 bit 1
CS32	= 2	; Clock Select3 bit 2
WGM32	= 3	; Waveform Generation Mode Bit 2
WGM33	= 4	; Waveform Generation Mode Bit 3
ICES3	= 6	; Input Capture 3 Edge Select
ICNC3	= 7	; Input Capture 3 Noise Canceler

; TCCR3C - Timer/Counter3 Control Register C
FOC3B	= 6	; Force Output Compare for Channel B
FOC3A	= 7	; Force Output Compare for Channel A

; OCR3BH - Timer/Counter3 Output Compare Register B High Byte
OCR3AH0	= 0	; Timer/Counter3 Output Compare Register High Byte bit 0
OCR3AH1	= 1	; Timer/Counter3 Output Compare Register High Byte bit 1
OCR3AH2	= 2	; Timer/Counter3 Output Compare Register High Byte bit 2
OCR3AH3	= 3	; Timer/Counter3 Output Compare Register High Byte bit 3
OCR3AH4	= 4	; Timer/Counter3 Output Compare Register High Byte bit 4
OCR3AH5	= 5	; Timer/Counter3 Output Compare Register High Byte bit 5
OCR3AH6	= 6	; Timer/Counter3 Output Compare Register High Byte bit 6
OCR3AH7	= 7	; Timer/Counter3 Output Compare Register High Byte bit 7

; OCR3BL - Timer/Counter3 Output Compare Register B Low Byte
OCR3AL0	= 0	; Timer/Counter3 Output Compare Register Low Byte Bit 0
OCR3AL1	= 1	; Timer/Counter3 Output Compare Register Low Byte Bit 1
OCR3AL2	= 2	; Timer/Counter3 Output Compare Register Low Byte Bit 2
OCR3AL3	= 3	; Timer/Counter3 Output Compare Register Low Byte Bit 3
OCR3AL4	= 4	; Timer/Counter3 Output Compare Register Low Byte Bit 4
OCR3AL5	= 5	; Timer/Counter3 Output Compare Register Low Byte Bit 5
OCR3AL6	= 6	; Timer/Counter3 Output Compare Register Low Byte Bit 6
OCR3AL7	= 7	; Timer/Counter3 Output Compare Register Low Byte Bit 7



; ***** WATCHDOG *********************
; WDTCSR - Watchdog Timer Control Register
WDP0	= 0	; Watch Dog Timer Prescaler bit 0
WDP1	= 1	; Watch Dog Timer Prescaler bit 1
WDP2	= 2	; Watch Dog Timer Prescaler bit 2
WDE	= 3	; Watch Dog Enable
WDCE	= 4	; Watchdog Change Enable
WDP3	= 5	; Watchdog Timer Prescaler Bit 3
WDIE	= 6	; Watchdog Timeout Interrupt Enable
WDIF	= 7	; Watchdog Timeout Interrupt Flag


; ***** JTAG *************************
; OCDR - On-Chip Debug Related Register in I/O Memory
OCDR0	= 0	; On-Chip Debug Register Bit 0
OCDR1	= 1	; On-Chip Debug Register Bit 1
OCDR2	= 2	; On-Chip Debug Register Bit 2
OCDR3	= 3	; On-Chip Debug Register Bit 3
OCDR4	= 4	; On-Chip Debug Register Bit 4
OCDR5	= 5	; On-Chip Debug Register Bit 5
OCDR6	= 6	; On-Chip Debug Register Bit 6
OCDR7	= 7	; On-Chip Debug Register Bit 7
IDRD	= OCDR7	; For compatibility

; MCUCR - MCU Control Register
JTD	= 7	; JTAG Interface Disable

; MCUSR - MCU Status Register
JTRF	= 4	; JTAG Reset Flag


; ***** BOOT_LOAD ********************
; SPMCSR - Store Program Memory Control Register
SPMEN	= 0	; Store Program Memory Enable
PGERS	= 1	; Page Erase
PGWRT	= 2	; Page Write
BLBSET	= 3	; Boot Lock Bit Set
RWWSRE	= 4	; Read While Write section read enable
SIGRD	= 5	; Signature Row Read
RWWSB	= 6	; Read While Write Section Busy
SPMIE	= 7	; SPM Interrupt Enable


; ***** EXTERNAL_INTERRUPT ***********
; EICRA - External Interrupt Control Register A
ISC00	= 0	; External Interrupt Sense Control Bit
ISC01	= 1	; External Interrupt Sense Control Bit
ISC10	= 2	; External Interrupt Sense Control Bit
ISC11	= 3	; External Interrupt Sense Control Bit
ISC20	= 4	; External Interrupt Sense Control Bit
ISC21	= 5	; External Interrupt Sense Control Bit

; EIMSK - External Interrupt Mask Register
INT0	= 0	; External Interrupt Request 0 Enable
INT1	= 1	; External Interrupt Request 1 Enable
INT2	= 2	; External Interrupt Request 2 Enable

; EIFR - External Interrupt Flag Register
INTF0	= 0	; External Interrupt Flag 0
INTF1	= 1	; External Interrupt Flag 1
INTF2	= 2	; External Interrupt Flag 2

; PCICR - Pin Change Interrupt Control Register
PCIE0	= 0	; Pin Change Interrupt Enable 0
PCIE1	= 1	; Pin Change Interrupt Enable 1
PCIE2	= 2	; Pin Change Interrupt Enable 2
PCIE3	= 3	; Pin Change Interrupt Enable 3

; PCIFR - Pin Change Interrupt Flag Register
PCIF0	= 0	; Pin Change Interrupt Flag 0
PCIF1	= 1	; Pin Change Interrupt Flag 1
PCIF2	= 2	; Pin Change Interrupt Flag 2
PCIF3	= 3	; Pin Change Interrupt Flag 3

; PCMSK3 - Pin Change Mask Register 3
PCINT24	= 0	; Pin Change Enable Mask 24
PCINT25	= 1	; Pin Change Enable Mask 25
PCINT26	= 2	; Pin Change Enable Mask 26
PCINT27	= 3	; Pin Change Enable Mask 27
PCINT28	= 4	; Pin Change Enable Mask 28
PCINT29	= 5	; Pin Change Enable Mask 29
PCINT30	= 6	; Pin Change Enable Mask 30
PCINT31	= 7	; Pin Change Enable Mask 31

; PCMSK2 - Pin Change Mask Register 2
PCINT16	= 0	; Pin Change Enable Mask 16
PCINT17	= 1	; Pin Change Enable Mask 17
PCINT18	= 2	; Pin Change Enable Mask 18
PCINT19	= 3	; Pin Change Enable Mask 19
PCINT20	= 4	; Pin Change Enable Mask 20
PCINT21	= 5	; Pin Change Enable Mask 21
PCINT22	= 6	; Pin Change Enable Mask 22
PCINT23	= 7	; Pin Change Enable Mask 23

; PCMSK1 - Pin Change Mask Register 1
PCINT8	= 0	; Pin Change Enable Mask 8
PCINT9	= 1	; Pin Change Enable Mask 9
PCINT10	= 2	; Pin Change Enable Mask 10
PCINT11	= 3	; Pin Change Enable Mask 11
PCINT12	= 4	; Pin Change Enable Mask 12
PCINT13	= 5	; Pin Change Enable Mask 13
PCINT14	= 6	; Pin Change Enable Mask 14
PCINT15	= 7	; Pin Change Enable Mask 15

; PCMSK0 - Pin Change Mask Register 0
PCINT0	= 0	; Pin Change Enable Mask 0
PCINT1	= 1	; Pin Change Enable Mask 1
PCINT2	= 2	; Pin Change Enable Mask 2
PCINT3	= 3	; Pin Change Enable Mask 3
PCINT4	= 4	; Pin Change Enable Mask 4
PCINT5	= 5	; Pin Change Enable Mask 5
PCINT6	= 6	; Pin Change Enable Mask 6
PCINT7	= 7	; Pin Change Enable Mask 7


; ***** AD_CONVERTER *****************
; ADMUX - The ADC multiplexer Selection Register
MUX0	= 0	; Analog Channel and Gain Selection Bits
MUX1	= 1	; Analog Channel and Gain Selection Bits
MUX2	= 2	; Analog Channel and Gain Selection Bits
MUX3	= 3	; Analog Channel and Gain Selection Bits
MUX4	= 4	; Analog Channel and Gain Selection Bits
ADLAR	= 5	; Left Adjust Result
REFS0	= 6	; Reference Selection Bit 0
REFS1	= 7	; Reference Selection Bit 1

; ADCSRA - The ADC Control and Status register A
ADPS0	= 0	; ADC  Prescaler Select Bits
ADPS1	= 1	; ADC  Prescaler Select Bits
ADPS2	= 2	; ADC  Prescaler Select Bits
ADIE	= 3	; ADC Interrupt Enable
ADIF	= 4	; ADC Interrupt Flag
ADATE	= 5	; ADC  Auto Trigger Enable
ADSC	= 6	; ADC Start Conversion
ADEN	= 7	; ADC Enable

; ADCSRB - The ADC Control and Status register B
ADTS0	= 0	; ADC Auto Trigger Source bit 0
ADTS1	= 1	; ADC Auto Trigger Source bit 1
ADTS2	= 2	; ADC Auto Trigger Source bit 2
;.equ	ACME	= 6	;

; ADCH - ADC Data Register High Byte
ADCH0	= 0	; ADC Data Register High Byte Bit 0
ADCH1	= 1	; ADC Data Register High Byte Bit 1
ADCH2	= 2	; ADC Data Register High Byte Bit 2
ADCH3	= 3	; ADC Data Register High Byte Bit 3
ADCH4	= 4	; ADC Data Register High Byte Bit 4
ADCH5	= 5	; ADC Data Register High Byte Bit 5
ADCH6	= 6	; ADC Data Register High Byte Bit 6
ADCH7	= 7	; ADC Data Register High Byte Bit 7

; ADCL - ADC Data Register Low Byte
ADCL0	= 0	; ADC Data Register Low Byte Bit 0
ADCL1	= 1	; ADC Data Register Low Byte Bit 1
ADCL2	= 2	; ADC Data Register Low Byte Bit 2
ADCL3	= 3	; ADC Data Register Low Byte Bit 3
ADCL4	= 4	; ADC Data Register Low Byte Bit 4
ADCL5	= 5	; ADC Data Register Low Byte Bit 5
ADCL6	= 6	; ADC Data Register Low Byte Bit 6
ADCL7	= 7	; ADC Data Register Low Byte Bit 7

; DIDR0 - Digital Input Disable Register
ADC0D	= 0	;
ADC1D	= 1	;
ADC2D	= 2	;
ADC3D	= 3	;
ADC4D	= 4	;
ADC5D	= 5	;
ADC6D	= 6	;
ADC7D	= 7	;


; ***** CPU **************************
; SREG - Status Register
SREG_C	= 0	; Carry Flag
SREG_Z	= 1	; Zero Flag
SREG_N	= 2	; Negative Flag
SREG_V	= 3	; Two's Complement Overflow Flag
SREG_S	= 4
SREG_H	= 5	; Half Carry Flag
SREG_T	= 6	; Bit Copy Storage
SREG_I	= 7	; Global Interrupt Enable

; MCUCR - MCU Control Register
IVCE	= 0	; Interrupt Vector Change Enable
IVSEL	= 1	; Interrupt Vector Select
PUD	= 4	; Pull-up disable
;.equ	JTD	= 7	; JTAG Interface Disable

; MCUSR - MCU Status Register
PORF	= 0	; Power-on reset flag
EXTRF	= 1	; External Reset Flag
BORF	= 2	; Brown-out Reset Flag
WDRF= 3	; Watchdog Reset Flag
;.equ	JTRF	= 4	; JTAG Reset Flag

; OSCCAL - Oscillator Calibration Value
CAL0	= 0	; Oscillator Calibration Value Bit0
CAL1	= 1	; Oscillator Calibration Value Bit1
CAL2	= 2	; Oscillator Calibration Value Bit2
CAL3	= 3	; Oscillator Calibration Value Bit3
CAL4	= 4	; Oscillator Calibration Value Bit4
CAL5	= 5	; Oscillator Calibration Value Bit5
CAL6	= 6	; Oscillator Calibration Value Bit6
CAL7	= 7	; Oscillator Calibration Value Bit7

; CLKPR -
CLKPS0	= 0	;
CLKPS1	= 1	;
CLKPS2	= 2	;
CLKPS3	= 3	;
CPKPCE	= 7	;

; SMCR - Sleep Mode Control Register
SE	= 0	; Sleep Enable
SM0	= 1	; Sleep Mode Select bit 0
SM1	= 2	; Sleep Mode Select bit 1
SM2	= 3	; Sleep Mode Select bit 2

; RAMPZ - RAM Page Z Select Register
RAMPZ0	= 0	; RAM Page Z Select Register Bit 0

; GPIOR2 - General Purpose IO Register 2
GPIOR20	= 0	; General Purpose IO Register 2 bit 0
GPIOR21	= 1	; General Purpose IO Register 2 bit 1
GPIOR22	= 2	; General Purpose IO Register 2 bit 2
GPIOR23	= 3	; General Purpose IO Register 2 bit 3
GPIOR24	= 4	; General Purpose IO Register 2 bit 4
GPIOR25	= 5	; General Purpose IO Register 2 bit 5
GPIOR26	= 6	; General Purpose IO Register 2 bit 6
GPIOR27	= 7	; General Purpose IO Register 2 bit 7

; GPIOR1 - General Purpose IO Register 1
GPIOR10	= 0	; General Purpose IO Register 1 bit 0
GPIOR11	= 1	; General Purpose IO Register 1 bit 1
GPIOR12	= 2	; General Purpose IO Register 1 bit 2
GPIOR13	= 3	; General Purpose IO Register 1 bit 3
GPIOR14	= 4	; General Purpose IO Register 1 bit 4
GPIOR15	= 5	; General Purpose IO Register 1 bit 5
GPIOR16	= 6	; General Purpose IO Register 1 bit 6
GPIOR17	= 7	; General Purpose IO Register 1 bit 7

; GPIOR0 - General Purpose IO Register 0
GPIOR00	= 0	; General Purpose IO Register 0 bit 0
GPIOR01	= 1	; General Purpose IO Register 0 bit 1
GPIOR02	= 2	; General Purpose IO Register 0 bit 2
GPIOR03	= 3	; General Purpose IO Register 0 bit 3
GPIOR04	= 4	; General Purpose IO Register 0 bit 4
GPIOR05	= 5	; General Purpose IO Register 0 bit 5
GPIOR06	= 6	; General Purpose IO Register 0 bit 6
GPIOR07	= 7	; General Purpose IO Register 0 bit 7

; PRR0 - Power Reduction Register0
PRADC	= 0	; Power Reduction ADC
PRUSART0	= 1	; Power Reduction USART
PRSPI	= 2	; Power Reduction Serial Peripheral Interface
PRTIM1	= 3	; Power Reduction Timer/Counter1
PRTIM0	= 5	; Power Reduction Timer/Counter0
PRTIM2	= 6	; Power Reduction Timer/Counter2
PRTWI	= 7	; Power Reduction TWI


; ***** TIMER_COUNTER_1 **************
; TIMSK1 - Timer/Counter1 Interrupt Mask Register
TOIE1	= 0	; Timer/Counter1 Overflow Interrupt Enable
OCIE1A	= 1	; Timer/Counter1 Output Compare A Match Interrupt Enable
OCIE1B	= 2	; Timer/Counter1 Output Compare B Match Interrupt Enable
ICIE1	= 5	; Timer/Counter1 Input Capture Interrupt Enable

; TIFR1 - Timer/Counter Interrupt Flag register
TOV1	= 0	; Timer/Counter1 Overflow Flag
OCF1A	= 1	; Timer/Counter1 Output Compare A Match Flag
OCF1B	= 2	; Timer/Counter1 Output Compare B Match Flag
ICF1	= 5	; Timer/Counter1 Input Capture Flag

; TCCR1A - Timer/Counter1 Control Register A
WGM10	= 0	; Pulse Width Modulator Select Bit 0
PWM10	= WGM10	; For compatibility
WGM11	= 1	; Pulse Width Modulator Select Bit 1
PWM11	= WGM11	; For compatibility
COM1B0	= 4	; Comparet Ouput Mode 1B, bit 0
COM1B1	= 5	; Compare Output Mode 1B, bit 1
COM1A0	= 6	; Comparet Ouput Mode 1A, bit 0
COM1A1	= 7	; Compare Output Mode 1A, bit 1

; TCCR1B - Timer/Counter1 Control Register B
CS10	= 0	; Clock Select bit 0
CS11	= 1	; Clock Select 1 bit 1
CS12	= 2	; Clock Select1 bit 2
WGM12	= 3	; Waveform Generation Mode Bit 2
CTC1	= WGM12	; For compatibility
WGM13	= 4	; Waveform Generation Mode Bit 3
ICES1	= 6	; Input Capture 1 Edge Select
ICNC1	= 7	; Input Capture 1 Noise Canceler

; TCCR1C - Timer/Counter1 Control Register C
FOC1B	= 6	; Force Output Compare for Channel B
FOC1A	= 7	; Force Output Compare for Channel A


; ***** EEPROM ***********************
; EEARH - EEPROM Address Register Low Byte
EEAR8	= 0	; EEPROM Read/Write Access Bit 8
EEAR9	= 1	; EEPROM Read/Write Access Bit 9
EEAR10	= 2	; EEPROM Read/Write Access Bit 10
EEAR11	= 3	; EEPROM Read/Write Access Bit 11

; EEARL - EEPROM Address Register Low Byte
EEAR0	= 0	; EEPROM Read/Write Access Bit 0
EEAR1	= 1	; EEPROM Read/Write Access Bit 1
EEAR2	= 2	; EEPROM Read/Write Access Bit 2
EEAR3	= 3	; EEPROM Read/Write Access Bit 3
EEAR4	= 4	; EEPROM Read/Write Access Bit 4
EEAR5	= 5	; EEPROM Read/Write Access Bit 5
EEAR6	= 6	; EEPROM Read/Write Access Bit 6
EEAR7	= 7	; EEPROM Read/Write Access Bit 7

; EEDR - EEPROM Data Register
EEDR0	= 0	; EEPROM Data Register bit 0
EEDR1	= 1	; EEPROM Data Register bit 1
EEDR2	= 2	; EEPROM Data Register bit 2
EEDR3	= 3	; EEPROM Data Register bit 3
EEDR4	= 4	; EEPROM Data Register bit 4
EEDR5	= 5	; EEPROM Data Register bit 5
EEDR6	= 6	; EEPROM Data Register bit 6
EEDR7	= 7	; EEPROM Data Register bit 7

; EECR - EEPROM Control Register
EERE	= 0	; EEPROM Read Enable
EEPE	= 1	; EEPROM Write Enable
EEMPE	= 2	; EEPROM Master Write Enable
EERIE	= 3	; EEPROM Ready Interrupt Enable
EEPM0	= 4	; EEPROM Programming Mode Bit 0
EEPM1	= 5	; EEPROM Programming Mode Bit 1


; ***** SPI **************************
; SPDR0 - SPI Data Register
SPDRB0	= 0	; SPI Data Register bit 0
SPDRB1	= 1	; SPI Data Register bit 1
SPDRB2	= 2	; SPI Data Register bit 2
SPDRB3	= 3	; SPI Data Register bit 3
SPDRB4	= 4	; SPI Data Register bit 4
SPDRB5	= 5	; SPI Data Register bit 5
SPDRB6	= 6	; SPI Data Register bit 6
SPDRB7	= 7	; SPI Data Register bit 7

; SPSR0 - SPI Status Register
SPI2X0	= 0	; Double SPI Speed Bit
WCOL0	= 6	; Write Collision Flag
SPIF0	= 7	; SPI Interrupt Flag
SPIF	= 7	; SPI Interrupt Flag
; SPCR0 - SPI Control Register
SPR00	= 0	; SPI Clock Rate Select 0
SPR10	= 1	; SPI Clock Rate Select 1
CPHA0	= 2	; Clock Phase
CPOL0	= 3	; Clock polarity
MSTR0	= 4	; Master/Slave Select
DORD0	= 5	; Data Order
SPE0	= 6	; SPI Enable
SPIE0	= 7	; SPI Interrupt Enable


; ***** TWI **************************
; TWAMR - TWI (Slave) Address Mask Register
TWAM0	= 1	;
TWAMR0	= TWAM0	; For compatibility
TWAM1	= 2	;
TWAMR1	= TWAM1	; For compatibility
TWAM2	= 3	;
TWAMR2	= TWAM2	; For compatibility
TWAM3	= 4	;
TWAMR3	= TWAM3	; For compatibility
TWAM4	= 5	;
TWAMR4	= TWAM4	; For compatibility
TWAM5	= 6	;
TWAMR5	= TWAM5	; For compatibility
TWAM6	= 7	;
TWAMR6	= TWAM6	; For compatibility

; TWBR - TWI Bit Rate register
TWBR0	= 0	;
TWBR1	= 1	;
TWBR2	= 2	;
TWBR3	= 3	;
TWBR4	= 4	;
TWBR5	= 5	;
TWBR6	= 6	;
TWBR7	= 7	;

; TWCR - TWI Control Register
TWIE	= 0	; TWI Interrupt Enable
TWEN	= 2	; TWI Enable Bit
TWWC	= 3	; TWI Write Collition Flag
TWSTO	= 4	; TWI Stop Condition Bit
TWSTA	= 5	; TWI Start Condition Bit
TWEA	= 6	; TWI Enable Acknowledge Bit
TWINT	= 7	; TWI Interrupt Flag

; TWSR - TWI Status Register
TWPS0	= 0	; TWI Prescaler
TWPS1	= 1	; TWI Prescaler
TWS3	= 3	; TWI Status
TWS4	= 4	; TWI Status
TWS5	= 5	; TWI Status
TWS6	= 6	; TWI Status
TWS7	= 7	; TWI Status

; TWDR - TWI Data register
TWD0	= 0	; TWI Data Register Bit 0
TWD1	= 1	; TWI Data Register Bit 1
TWD2	= 2	; TWI Data Register Bit 2
TWD3	= 3	; TWI Data Register Bit 3
TWD4	= 4	; TWI Data Register Bit 4
TWD5	= 5	; TWI Data Register Bit 5
TWD6	= 6	; TWI Data Register Bit 6
TWD7	= 7	; TWI Data Register Bit 7

; TWAR - TWI (Slave) Address register
TWGCE	= 0	; TWI General Call Recognition Enable Bit
TWA0	= 1	; TWI (Slave) Address register Bit 0
TWA1	= 2	; TWI (Slave) Address register Bit 1
TWA2	= 3	; TWI (Slave) Address register Bit 2
TWA3	= 4	; TWI (Slave) Address register Bit 3
TWA4	= 5	; TWI (Slave) Address register Bit 4
TWA5	= 6	; TWI (Slave) Address register Bit 5
TWA6	= 7	; TWI (Slave) Address register Bit 6



; ***** LOCKSBITS ********************************************************
LB1	= 0	; Lock bit
LB2	= 1	; Lock bit
BLB01	= 2	; Boot Lock bit
BLB02	= 3	; Boot Lock bit
BLB11	= 4	; Boot lock bit
BLB12	= 5	; Boot lock bit


; ***** FUSES ************************************************************
; LOW fuse bits
CKSEL0	= 0	; Select Clock Source
CKSEL1	= 1	; Select Clock Source
CKSEL2	= 2	; Select Clock Source
CKSEL3	= 3	; Select Clock Source
SUT0	= 4	; Select start-up time
SUT1	= 5	; Select start-up time
CKOUT	= 6	; Clock output
CLKDIV8	= 7	; Divide clock by 8

; HIGH fuse bits
BOOTRST	= 0	; Select Reset Vector
BOOTSZ0	= 1	; Select Boot Size
BOOTSZ1	= 2	; Select Boot Size
EESAVE	= 3	; EEPROM memory is preserved through chip erase
WDTON	= 4	; Watchdog timer always on
SPIEN	= 5	; Enable Serial programming and Data Downloading
JTAGEN	= 6	; Enable JTAG
OCDEN	= 7	; Enable OCD

; EXTENDED fuse bits
BODLEVEL0	= 0	; Brown-out Detector trigger level
BODLEVEL1	= 1	; Brown-out Detector trigger level
BODLEVEL2	= 2	; Brown-out Detector trigger level





[DEF]
XL	=r26
XH	=r27
YL	=r28
YH	=r29
ZL	=r30
ZH	=r31


[INTS]
INT0=$002	;External Interrupt0 Vector Address
INT1=$004	;External Interrupt1 Vector Address
INT2=$006	;External Interrupt1 Vector Address
PCINT0=$008     ;Pin Change Interrupt Request 0
PCINT1=$00A     ;Pin Change Interrupt Request 1
PCINT2=$00C     ;Pin Change Interrupt Request 2
PCINT3=$00E     ;Pin Change Interrupt Request 3
WDT=$010        ;Watchdog Time-out Interrupt
OC2A =$012	;Timer2 compare match A Vector Address
OC2B =$014	;Timer2 compare match B Vector Address
OVF2=$016	;Timer2 overflow Vector Address
ICP1=$018	;Timer1 Input Capture Vector Address
OC1A=$01A	;Timer1 Output Compare A Interrupt Vector Address
OC1B=$01C	;Timer1 Output Compare B Interrupt Vector Address
OVF1=$01E	;Overflow1 Interrupt Vector Address
OC0A =$020	;Timer0 compare match Vector Address
OC0B =$022	;Timer0 compare match Vector Address
OVF0=$024	;Overflow0 Interrupt Vector Address
SPI =$026	;SPI Interrupt Vector Address
URXC=$028	;UART Receive Complete Interrupt Vector Address
UDRE=$02A	;UART Data Register Empty Interrupt Vector Address
UTXC=$02C	;UART Transmit Complete Interrupt Vector Address
ACI =$02E	;Analog Comparator Interrupt Vector Address
ADCC=$030	;ADC Conversion Complete Interrupt Vector Address
ERDY=$032	;EEPROM Write Complete Interrupt Vector Address
TWI=$034       ;2wire serial int
SPMR=$036	; Store Program Memory Ready Interrupt Vector Address
URXC1=$038	;UART 1 Receive Complete Interrupt Vector Address
UDRE1=$03A	;UART 1 Data Register Empty Interrupt Vector Address
UTXC1=$03C	;UART 1 Transmit Complete Interrupt Vector Address


; LAINTS:INT0,INT1,INT2
[INTLIST]
count=34
INTname1=INT0,$002,EIMSK.INT0,EIFR.INTF0
INTname2=INT1,$004,EIMSK.INT1,EIFR.INTF1
INTname3=INT2,$006,EIMSK.INT2,EIFR.INTF2
INTname4=PCINT0,$008,PCICR.PCIE0,PCIFR.PCIF0
INTname5=PCINT1,$00A,PCICR.PCIE1,PCIFR.PCIF1
INTname6=PCINT2,$00C,PCICR.PCIE2,PCIFR.PCIF2
INTname7=PCINT3,$00E,PCICR.PCIE3,PCIFR.PCIF3
INTname8=WDT@WATCHDOG,$010,WDTCSR.WDIE,WDTCSR.WDIF
INTname9=OC2A@COMPARE2A,$012,TIMSK2.OCIE2A,TIFR2.OCF2A
INTname10=OC2B@COMPARE2B,$014,TIMSK2.OCIE2B,TIFR2.OCF2B
INTname11=OVF2@TIMER2,$016,TIMSK2.TOIE2,TIFR2.TOV2
INTname12=ICP1@CAPTURE1,$018,TIMSK1.ICIE1,TIFR1.ICF1
INTname13=OC1A@COMPARE1A,$01A,TIMSK1.OCIE1A,TIFR1.OCF1A
INTname14=OC1B@COMPARE1B,$01C,TIMSK1.OCIE1B,TIFR1.OCF1B
INTname15=OVF1@TIMER1,$01E,TIMSK1.TOIE1,TIFR1.TOV1
INTname16=OC0A@COMPARE0A,$020,TIMSK0.OCIE0A,TIFR0.OCF0A
INTname17=OC0B@COMPARE0B,$022,TIMSK0.OCIE0B,TIFR0.OCF0B
INTname18=OVF0@TIMER0,$024,TIMSK0.TOIE0,TIFR0.TOV0
INTname19=SPI,$026,SPCR0.SPIE0,SPSR0.SPIF0
INTname20=URXC@SERIAL,$028,UCSR0B.RXCIE0,UCSR0A.RXC0
INTname21=UDRE,$02A,UCSR0B.UDRIE0,UCSR0A.UDRE0
INTname22=UTXC,$02C,UCSR0B.TXCIE0,UCSR0A.TXC0
INTname23=ACI,$02E,ACSR.ACIE,ACSR.ACI
INTname24=ADCC@ADC,$030,ADCSR.ADIE,ADCSR.ADIF
INTname25=ERDY,$032,EECR.EERIE
INTname26=TWI,$034,TWCR.TWIE,TWCR.TWINT
INTname27=SPMR,$036,SPMCSR.SPMIE
INTname28=URXC1@SERIAL1,$038,UCSR1B.RXCIE1,UCSR1A.RXC1
INTname29=UDRE1,$03A,UCSR1B.UDRIE1,UCSR1A.UDRE1
INTname30=UTXC1,$03C,UCSR1B.TXCIE1,UCSR1A.TXC1
INTname31=ICP3@CAPTURE3,$03E,TIMSK3.ICIE1,TIFR1.ICF1
INTname32=OC3A@COMPARE3A,$040,TIMSK3.OCIE3A,TIFR3.OCF3A
INTname33=OC3B@COMPARE3B,$042,TIMSK3.OCIE3B,TIFR3.OCF3B
INTname34=OVF3@TIMER3,$044,TIMSK3.TOIE3,TIFR3.TOV3


[I2CSLAVE]
POSSIBLE=NO    ; software slave mode not possible , BUT TWI slave mode is possible

[WIO]
UBRR0	= $c4	; MEMORY MAPPED
UBRR=$C4
OCR1B	= $8a	; MEMORY MAPPED
PWM1B=$8A
OCR1A	= $88	; MEMORY MAPPED
PWM1A=$88
ICR1	= $86	; MEMORY MAPPED
TCNT1	= $84	; MEMORY MAPPED
ADC	= $78	; MEMORY MAPPED
SP	= $3d
EEAR	= $21
COMPARE1B=$8a	; MEMORY MAPPED
PWM1B=$8A
COMPARE1A=$88	; MEMORY MAPPED
CAPTURE1=$86	; MEMORY MAPPED
TIMER1=$84	; MEMORY MAPPED
COMPARE3B=$9a	; MEMORY MAPPED
PWM3B=$9A
COMPARE3A=$98	; MEMORY MAPPED
PWM3A=$98
OCR3A=$98
CAPTURE3=$96	; MEMORY MAPPED
TIMER3=$94	; MEMORY MAPPED
ICR3=$96	; MEMORY MAPPED
TCNT3=$94       ; MEMORY MAPPED

[stk500]
chip_erase_delay=9000
flags=8
timeout=200
stabdelay=100
cmdexedelay=25
synchloops=32
bytedelay=0
pollindex=3
pollvalue=83
predelay=1
postdelay=1
pollmethod=1
pgm_enable=1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 1 x x x x x x x x x x x x x x x x
chip_erase=1 0 1 0 1 1 0 0 1 0 0 x x x x x x x x x x x x x x x x x x x x x

[stk500\flash]
paged=1
page_size=256
num_pages=512
min_write_delay=4500
max_write_delay=4500
readback_p1=255
readback_p2=255
mode=65
delay=10
blocksize=256
readsize=256
pollindex=3
read_lo=0 0 1 0 0 0 0 0 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 o o o o o o o o
read_hi=0 0 1 0 1 0 0 0 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 o o o o o o o o
loadpage_lo=0 1 0 0 0 0 0 0 0 0 x x x x x x x a6 a5 a4 a3 a2 a1 a0 i i i i i i i i
loadpage_hi=0 1 0 0 1 0 0 0 0 0 x x x x x x x a6 a5 a4 a3 a2 a1 a0 i i i i i i i i
writepage=0 1 0 0 1 1 0 0 a15 a14 a13 a12 a11 a10 a9 a8 a7 x x x x x x x x x x x x x x x

[stk500\eeprom]
paged=0
page_size=8
num_pages=0
min_write_delay=9000
max_write_delay=9000
readback_p1=255
readback_p2=255
mode=4
delay=10
blocksize=64
readsize=256
read=1 0 1 0 0 0 0 0 0 0 x x x x a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 o o o o o o o o
write=1 1 0 0 0 0 0 0 0 0 x x x x a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 i i i i i i i i
loadpage_lo=1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 a1 a0 i i i i i i i i
writepage=1 1 0 0 0 0 1 0 0 0 x x x x a9 a8 a7 a6 a5 a4 a3 a2 0 0 x x x x x x x x


[CONFIG-1WIRE]
SECTION=1WIRE
OPTIONCOUNT=5
OPTION1=1WIRE
OPTION1VALUE=#PORT
OPTION2=EXTENDED
OPTION2VALUE=[0,1,2]
OPTION3=DRIVE
OPTION3VALUE=#PORT
OPTION4=DPU
OPTION4VALUE=#PORT
OPTION5=SPU
OPTION5VALUE=#PORT

[CONFIG-ACI]
SECTION=ACI
OPTIONCOUNT=4
OPTION1=ACI
OPTION1VALUE=[ON,OFF]
OPTION2=COMPARE
OPTION2VALUE=[ON,OFF]
OPTION3=TRIGGER
OPTION3VALUE=[TOGGLE,RISING,FALLING]
OPTION4=BANDGAP
OPTION4VALUE=[ENABLED,DISABLED]

[CONFIG-ADC]
SECTION=ADC
OPTIONCOUNT=3
OPTION1=ADC
OPTION1VALUE=[SINGLE,FREE]
OPTION2=PRESCALER
OPTION2VALUE=[1-2,4,8,16,32,64,128,AUTO]
OPTION3=REFERENCE
OPTION3VALUE=[OFF,AVCC,INTERNAL,INTERNAL_1.1,INTERNAL_2.56]

[CONFIG-ATEMU]
SECTION=ATEMU
OPTIONCOUNT=4
OPTION1=ATEMU
OPTION1VALUE=[INT0,INT1,INT2]
OPTION2=DATA
OPTION2VALUE=#PIN
OPTION3=CLOCK
OPTION3VALUE=#PIN
OPTION4=INIT
OPTION4VALUE=[&HAB83]

[CONFIG-BASE]
SECTION=BASE
OPTIONCOUNT=1
OPTION1=BASE
OPTION1VALUE=[0,1]
OPTION1CODE=CONST _BASE=%1


[CONFIG-BCCARD]
SECTION=BCCARD
OPTIONCOUNT=3
OPTION1=BCCARD
OPTION1VALUE=#PORTS
OPTION1CODE=DIM _BC_PCB as byte,Sw1 As Byte,Sw2 As Byte
OPTION2=IO
OPTION2VALUE=[0,1,2,3,4,5,6,7]
OPTION3=RESET
OPTION3VALUE=[0,1,2,3,4,5,6,7]

[CONFIG-CLOCK]
SECTION=CLOCK
OPTIONCOUNT=2
OPTION1=CLOCK
OPTION1VALUE=[SOFT,USER]
OPTION1CODE=Dim _sec as byte, _min as byte, _hour as byte, _day as byte, _month as byte, _year as byte,Date$ As String * 8 , Time$ As String * 8
OPTION2=GOSUB
OPTION2VALUE=[SECTIC]



[CONFIG-COM1]
SECTION=COMMUNICATION\COM1
OPTIONCOUNT=6
OPTION1=COM1
OPTION1VALUE=[dummy,75,150,300,600,1200,2400,4800,9600,19200,38400,57600,115200,250000,500000,0-1000000]
OPTION2=SYNCHRONE
OPTION2VALUE=[0,1]
OPTION3=PARITY
OPTION3VALUE=[NONE,EVEN,ODD]
OPTION4=STOPBITS
OPTION4VALUE=[1,2]
OPTION5=DATABITS
OPTION5VALUE=[4,5,7,8,9]
OPTION6=CLOCKPOL
OPTION6VALUE=[0,1]

[CONFIG-COM2]
SECTION=COMMUNICATION\COM2
OPTIONCOUNT=6
OPTION1=COM2
OPTION1VALUE=[dummy,75,150,300,600,1200,2400,4800,9600,19200,38400,57600,115200,250000,500000,0-1000000]
OPTION2=SYNCHRONE
OPTION2VALUE=[0,1]
OPTION3=PARITY
OPTION3VALUE=[NONE,EVEN,ODD]
OPTION4=STOPBITS
OPTION4VALUE=[1,2]
OPTION5=DATABITS
OPTION5VALUE=[4,5,7,8,9]
OPTION6=CLOCKPOL
OPTION6VALUE=[0,1]

[CONFIG-CLOCKDIV]
SECTION=CLOCKDIV
OPTIONCOUNT=1
OPTION1=CLOCKDIV
OPTION1VALUE=[1,2,4,8,16,32,64,128,256]

[CONFIG-DATE]
SECTION=DATE
OPTIONCOUNT=2
OPTION1=DATE
OPTION1VALUE=[MDY,YMD,DMY]
OPTION2=SEPARATOR
OPTION2VALUE=[SLASH,MINUS,DOT]


[CONFIG-DCF77]
SECTION=DCF77
OPTIONCOUNT=13
OPTION1=DCF77
OPTION1VALUE=#PIN
OPTION2=TIMER
OPTION2VALUE=[0,1]
OPTION3=INVERTED
OPTION3VALUE=[0,1]
OPTION4=CHECK
OPTION4VALUE=[0,1,2]
OPTION5=UPDATE
OPTION5VALUE=[0,1,2]
OPTION6=UPDATETIME
OPTION6VALUE=[0-59]
OPTION7=TIMER1SEC
OPTION7VALUE=[0,1]
OPTION8=SWITCHPOWER
OPTION8VALUE=[0,1]
OPTION9=POWERPIN
OPTION9VALUE=#PIN
OPTION10=POWERLEVEL
OPTION10VALUE=[0,1]
OPTION11=SECONDTICKS
OPTION11VALUE=[0-59]
OPTION12=DEBUG
OPTION12VALUE=[0,1]
OPTION13=GOSUB
OPTION13VALUE=SECTIC

[CONFIG-DEBOUNCE]
SECTION=DEBOUNCE
OPTIONCOUNT=1
OPTION1=DEBOUNCE
OPTION1VALUE=[1-65535]

[CONFIG-DMXSLAVE]
SECTION=DMXSLAVE
OPTIONCOUNT=4
OPTION1=DMXSLAVE
OPTION1VALUE=[COM1,COM2]
OPTION1CODE=Dim _dmxcount As Word,_dmx_address As Word,_dmx_stored_counter As Word,_dmx_channels_toget As Word,_dmx_sync As Byte,_dmx_received(%2) As Byte:Const _dmx_channels=%2
OPTION2=CHANNELS
OPTION2VALUE=[1-512]
OPTION3=DMXSTART
OPTION3VALUE=[1-512]
OPTION4=STORE
OPTION4VALUE=[1-512]

[CONFIG-DP]
SECTION=DP
OPTIONCOUNT=1
OPTION1=DP
OPTION1VALUE=[DOT,COMMA]


[CONFIG-EXTENDED]
SECTION=EXTENDED_PORT
OPTIONCOUNT=1
OPTION1=EXTENDED_PORT
OPTION1VALUE=[WARNING,ERROR]

[CONFIG-FT800]
SECTION=FT800
OPTIONCOUNT=10
OPTION1=FT800
OPTION1VALUE=[SPI]
OPTION2=FTCS
OPTION2VALUE=#PORT
OPTION3=FTPD
OPTION3VALUE=#PORT
OPTION4=FTSAVE
OPTION4VALUE=[0,1]
OPTION4CODE=CONST _FTSAVE=%FTSAVE
OPTION5=FTDEBUG
OPTION5VALUE=[0,1]
OPTION5CODE=CONST _FTDEBUG=%FTDEBUG
OPTION6=FTCHIP
OPTION6VALUE=[800,801]
OPTION6CODE=CONST FT_CHIP=%FTCHIP
OPTION7=PLATFORM
OPTION7VALUE=[EVE,GAMEDUINO2]
OPTION7CODE=CONST FT_PLATFORM=%PLATFORM
OPTION8=LCD_SCREEN
OPTION8VALUE=[480272,320240]
OPTION8CODE=CONST FT_LCDSCREEN=%LCD_SCREEN
OPTION9=LCD_ROTATE
OPTION9VALUE=[0,1]
OPTION9CODE=CONST FT_ROTATEDISPLAY=[0,1]
OPTION10=LCD_CALIBRATION
OPTION10VALUE=[0,1]
OPTION10CODE=CONST FT_LCDCAL=[0,1]

[CONFIG-GRAPHLCD]
SECTION=GRAPHLCD
OPTIONCOUNT=14
OPTION1=GRAPHLCD
OPTION1VALUE=[240X64,128X128,128X64,160X48,240X128,192X64,SED180X32,128X64sed,120X64sed,Color,128X64EADOGM,122X32SED,320X240SED1330,192X64SED,320X240FSA506]
OPTION2=DATAPORT
OPTION2VALUE=#PORTS
OPTION3=CONTROLPORT
OPTION3VALUE=#PORTS
OPTION4=CE
OPTION4VALUE=[0-7]
OPTION5=CD
OPTION5VALUE=[0-7]
OPTION6=WR
OPTION6VALUE=[0-7]
OPTION7=RD
OPTION7VALUE=[0-7]
OPTION8=FS
OPTION8VALUE=[0-7]
OPTION9=RESET
OPTION9VALUE=[0-7]
OPTION10=MODE
OPTION10VALUE=[6,8]
OPTION11=CS1
OPTION11VALUE=[0-7]
OPTION12=A0
OPTION12VALUE=[0-7]
OPTION13=SI
OPTION13VALUE=[0-7]
OPTION14=SCLK
OPTION14VALUE=[0-7]

[CONFIG-HITAG]
SECTION=HITAG
OPTIONCOUNT=7
OPTION1=HITAG
OPTION1VALUE=64
OPTION2=TYPE
OPTION2VALUE=[HTRC110,EM4095]
OPTION3=DOUT
OPTION3VALUE=#PIN
OPTION4=DIN
OPTION4VALUE=#PIN
OPTION5=CLOCK
OPTION5VALUE=#PIN
OPTION6=INT
OPTION6VALUE=[INT0,INT1,INT2]
OPTION7=DEMOD
OPTION7VALUE=#PIN

[CONFIG-I2CBUS]
SECTION=I2C\I2CBUS
OPTIONCOUNT=3
OPTION1=I2CBUS
OPTION1CODE=DIM I2CBUS AS BYTE
OPTION1VALUE=[0-15]
OPTION2=SCL
OPTION2VALUE=#PORT
OPTION3=SDA
OPTION3VALUE=#PORT

[CONFIG-I2CDELAY]
SECTION=I2C\I2CDELAY
OPTIONCOUNT=1
OPTION1=I2CDELAY
OPTION1VALUE=[1-255]

[CONFIG-SCL]
SECTION=I2C\SCL
OPTIONCOUNT=1
OPTION1=SCL
OPTION1VALUE=#PORT

[CONFIG-SDA]
SECTION=I2C\SDA
OPTIONCOUNT=1
OPTION1=SDA
OPTION1VALUE=#PORT

[CONFIG-I2CSLAVE]
SECTION=I2C\I2CSLAVE
OPTIONCOUNT=3
OPTION1=I2CSLAVE
OPTION1VALUE=[0-255]
OPTION2=INT
OPTION2VALUE=[INT0,INT1,INT2]
OPTION3=TIMER
OPTION3VALUE=[0-2]

[CONFIG-INPUT1]
SECTION=COMMUNICATION\INPUT1
OPTIONCOUNT=2
OPTION1=INPUT1
OPTION1VALUE=[CR,LF,CRLF,LFCR]
OPTION2=ECHO
OPTION2VALUE=[CR,LF,CRLF,LFCR]

[CONFIG-INT0]
SECTION=INTERRUPTS\INT0
OPTIONCOUNT=1
OPTION1=INT0
OPTION1VALUE=[RISING,FALLING,LOW_LEVEL,CHANGE]

[CONFIG-INT1]
SECTION=INTERRUPTS\INT1
OPTIONCOUNT=1
OPTION1=INT1
OPTION1VALUE=[RISING,FALLING,LOW_LEVEL,CHANGE]

[CONFIG-INT2]
SECTION=INTERRUPTS\INT2
OPTIONCOUNT=1
OPTION1=INT2
OPTION1VALUE=[RISING,FALLING,LOW_LEVEL,CHANGE]

[CONFIG-INT3]
SECTION=INTERRUPTS\INT3
OPTIONCOUNT=1
OPTION1=INT3
OPTION1VALUE=[RISING,FALLING,LOW_LEVEL,CHANGE]

[CONFIG-INT4]
SECTION=INTERRUPTS\INT4
OPTIONCOUNT=1
OPTION1=INT4
OPTION1VALUE=[RISING,FALLING,LOW_LEVEL,CHANGE]

[CONFIG-KBD]
SECTION=KBD
OPTIONCOUNT=4
OPTION1=KBD
OPTION1VALUE=#PORTS
OPTION2=DEBOUNCE
OPTION2VALUE=[1-255]
OPTION3=DELAY
OPTION3VALUE=[1-255]
OPTION4=COLS
OPTION4VALUE=[2,3,4]

[CONFIG-KEYBOARD]
SECTION=KEYBOARD
OPTIONCOUNT=3
OPTION1=KEYBOARD
OPTION1VALUE=#PIN
OPTION2=DATA
OPTION2VALUE=#PIN
OPTION3=KEYDATA
OPTION3VALUE=#LABEL

[CONFIG-LCD]
SECTION=LCD\LCD
OPTIONCOUNT=3
OPTION1=LCD
OPTION1VALUE=[16x1,16x1a,16x2,16x3,16x4,20x2,20x4,20x4a,20x4VFD,40x2,40x4]
OPTION2=CHIPSET
OPTION2VALUE=[KS077,DOGM163V5,DOG163V3,DOG162V5,DOG162V3]
OPTION3=CONTRAST
OPTION3VALUE=[0-255]

[CONFIG-LCDBUS]
SECTION=LCD\LCDBUS
OPTIONCOUNT=1
OPTION1=LCDBUS
OPTION1VALUE=[4,8]

[CONFIG-LCDMODE]
SECTION=LCD\LCDMODE
OPTIONCOUNT=1
OPTION1=LCDMODE
OPTION1VALUE=[PORT,BUS]

[CONFIG-LCDPIN]
SECTION=LCD\LCDPIN
OPTIONCOUNT=15
OPTION1=LCDPIN
OPTION1VALUE=[PIN]
OPTION2=DB4
OPTION2VALUE=#PORT
OPTION3=DB5
OPTION3VALUE=#PORT
OPTION4=DB6
OPTION4VALUE=#PORT
OPTION5=DB7
OPTION5VALUE=#PORT
OPTION6=E
OPTION6VALUE=#PORT
OPTION7=E2
OPTION7VALUE=#PORT
OPTION8=RS
OPTION8VALUE=#PORT
OPTION9=WR
OPTION9VALUE=#PORT
OPTION10=RESET
OPTION10VALUE=#PORT
OPTION11=PORT
OPTION11VALUE=#PORTS
OPTION12=EDURATION
OPTION12VALUE=[0-255]
OPTION13=EDELAY
OPTION13VALUE=[0-255]
OPTION14=RESET
OPTION14VALUE=#PORT
OPTION15=MODE
OPTION15VALUE=[0,1]

[CONFIG-ports]
SECTION=PORTS\PORT#
OPTIONCOUNT=1
OPTION1=PORT#
OPTION1VALUE=[INPUT,OUTPUT,0-255]

[CONFIG-POWERMODE]
SECTION=POWERMODE
OPTIONCOUNT=1
OPTION1=POWERMODE
OPTION1VALUE=Idle,PowerDown,Standby,ADCnoice,PowerSave


[CONFIG-PRINT0]
SECTION=COMMUNICATION\PRINT0
OPTIONCOUNT=2
OPTION1=PRINT0
OPTION1VALUE=#PORT
OPTION2=MODE
OPTION2VALUE=[SET,RESET]

[CONFIG-PRINT1]
SECTION=COMMUNICATION\PRINT1
OPTIONCOUNT=2
OPTION1=PRINT1
OPTION1VALUE=#PORT
OPTION2=MODE
OPTION2VALUE=[SET,RESET]

[CONFIG-PRINTBIN]
SECTION=COMMUNICATION\PRINTBIN
OPTIONCOUNT=1
OPTION1=PRINTBIN
OPTION1VALUE=[EXTENDED]

[CONFIG-PS2EMU]
SECTION=PS2EMU
OPTIONCOUNT=3
OPTION1=PS2EMU
OPTION1VALUE=[INT0,INT1]
OPTION2=DATA
OPTION2VALUE=#PIN
OPTION3=CLOCK
OPTION3VALUE=#PIN

[CONFIG-RC5]
SECTION=RC5
OPTIONCOUNT=5
OPTION1=RC5
OPTION1VALUE=#PIN
OPTION2=MODE
OPTION2VALUE=[NORMAL,BACKGROUND]
OPTION3PARENT=OPTION2
OPTION3PARENTVALUE=BACKGROUND
OPTION3=TIMER
OPTION3VALUE=[1]
OPTION3CODE=Dim _rc5_bits As Byte, _rc5_bit_nr As Byte,Rc5 As Word,Rc5_command As Byte At Rc5 Overlay,Rc5_address As Byte At Rc5 + 1 Overlay
OPTION4PARENT=OPTION2
OPTION4PARENTVALUE=NORMAL
OPTION4VALUE=[0,2]
OPTION5=WAIT
OPTION5VALUE=[0-65535]


[CONFIG-SERIALIN0]
SECTION=COMMUNICATION\SERIALIN0
OPTIONCOUNT=7
OPTION1=SERIALIN0
OPTION1VALUE=[BUFFERED]
OPTION2=SIZE
OPTION2VALUE=[2-255]
OPTION3=BYTEMATCH
OPTION3VALUE=[ALL,NONE,0-255]
OPTION4=CTS
OPTION4VALUE=#PIN
OPTION5=RTS
OPTION5VALUE=#PIN
OPTION6=THRESHOLD_FULL
OPTION6VALUE=[1-255]
OPTION7=THRESHOLD_EMPTY
OPTION7VALUE=[1-255]

[CONFIG-SERIALOUT0]
SECTION=COMMUNICATION\SERIALOUT0
OPTIONCOUNT=2
OPTION1=SERIALOUT0
OPTION1VALUE=[BUFFERED]
OPTION2=SIZE
OPTION2VALUE=[1-255]

[CONFIG-SERVOS]
SECTION=SERVOS
OPTIONCOUNT=7
OPTION1=SERVOS
OPTION1VALUE=[1-255]
OPTION1CODE=DIM SERVO(%1) AS BYTE
OPTION2=SERVO1
OPTION2VALUE=#PORT
OPTION3=SERVO2
OPTION3VALUE=#PORT
OPTION4=SERVO3
OPTION4VALUE=#PORT
OPTION5=SERVO4
OPTION5VALUE=#PORT
OPTION6=RELOAD
OPTION6VALUE=[1-255]
OPTION7=INTERVAL
OPTION7VALUE=[1-255]

[CONFIG-SUBMODE]
SECTION=SUBMODE
OPTIONCOUNT=1
OPTION1=SUBMODE
OPTION1VALUE=[NEW,OLD]

[CONFIG-SHIFT]
SECTION=SHIFTIN
OPTIONCOUNT=1
OPTION1=SHIFTIN
OPTION1VALUE=[COMPATIBLE,NEW]

[CONFIG-SINGLE]
SECTION=SINGLE
OPTIONCOUNT=2
OPTION1=SINGLE
OPTION1VALUE=[SCIENTIFIC]
OPTION2=DIGITS
OPTION2VALUE=[0,1,2,3,4,5,6,7]


[CONFIG-SPI]
SECTION=SPI\SPI
OPTIONCOUNT=17
OPTION1=SPI
OPTION1VALUE=[HARD,SOFT]
OPTION2=INTERRUPT
OPTION2VALUE=[ON,OFF]
OPTION2PARENT=OPTION1
OPTION2PARENTVALUE=HARD
OPTION3=DATA_ORDER
OPTION3VALUE=[LSB,MSB]
OPTION3PARENT=OPTION1
OPTION3PARENTVALUE=HARD
OPTION4=MASTER
OPTION4VALUE=[YES,NO]
OPTION4PARENT=OPTION1
OPTION4PARENTVALUE=HARD
OPTION5=POLARITY
OPTION5VALUE=[HIGH,LOW]
OPTION5PARENT=OPTION1
OPTION5PARENTVALUE=HARD
OPTION6=PHASE
OPTION6VALUE=[0,1]
OPTION6PARENT=OPTION1
OPTION6PARENTVALUE=HARD
OPTION7=CLOCKRATE
OPTION7VALUE=[4,16,64,128]
OPTION7PARENT=OPTION1
OPTION7PARENTVALUE=HARD
OPTION8=NOSS
OPTION8VALUE=[0,1]
OPTION8PARENT=OPTION1
OPTION8PARENTVALUE=HARD
OPTION9=SPIIN
OPTION9VALUE=[0-255]
OPTION9PARENT=OPTION1
OPTION9PARENTVALUE=HARD
;
OPTION10=DIN
OPTION10VALUE=#PIN
OPTION10PARENT=OPTION1
OPTION10PARENTVALUE=SOFT
OPTION11=DOUT
OPTION11VALUE=#PORT
OPTION11PARENT=OPTION1
OPTION11PARENTVALUE=SOFT
OPTION12=SS
OPTION12VALUE=[NONE,#PORT]
OPTION12PARENT=OPTION1
OPTION12PARENTVALUE=SOFT
OPTION13=CLOCK
OPTION13VALUE=#PORT
OPTION13PARENT=OPTION1
OPTION13PARENTVALUE=SOFT
OPTION14=SPIIN
OPTION14VALUE=[0-255]
OPTION14PARENT=OPTION1
OPTION14PARENTVALUE=SOFT
OPTION15=MODE
OPTION15VALUE=[0,1,2,3]
OPTION15PARENT=OPTION1
OPTION15PARENTVALUE=SOFT
OPTION16=SPEED
OPTION16VALUE=[1-255]
OPTION16PARENT=OPTION1
OPTION16PARENTVALUE=SOFT
OPTION17=SETUP
OPTION17VALUE=[1-255]
OPTION17PARENT=OPTION1
OPTION17PARENTVALUE=SOFT

[CONFIG-TCPIP]
SECTION=TCPIP
OPTIONCOUNT=13
OPTION1=TCPIP
OPTION1VALUE=[INT0,INT1]
OPTION2=MAC
OPTION3=IP
OPTION4=SUBMASK
OPTION5=GATEWAY
OPTION6=LOCALPORT
OPTION6VALUE=[1-65535]
OPTION7=TX
OPTION8=RX
OPTION9=NOINIT
OPTION9VALUE=[0,1]
OPTION10=TWI
OPTION10VALUE=[0-255]
OPTION11=CLOCK
OPTION11VALUE=[100000,400000]
OPTION12=BASEADDRESS
OPTION13=TIMEOUT

[CONFIG-TIMER0]
SECTION=TIMERS\TIMER0
OPTIONCOUNT=4
OPTION1=TIMER0
OPTION1VALUE=[TIMER,COUNTER]
OPTION2=PRESCALE
OPTION2VALUE=[1,8,64,256,1024]
OPTION3=EDGE
OPTION3VALUE=[RISING,FALLING]
OPTION4=CLEAR TIMER
OPTION4VALUE=[1,0]

[CONFIG-TIMER1]
SECTION=TIMERS\TIMER1
OPTIONCOUNT=4
OPTION1=TIMER1
OPTION1VALUE=[TIMER,COUNTER]
OPTION2=PRESCALE
OPTION2VALUE=[1,8,64,256,1024]
OPTION3=EDGE
OPTION3VALUE=[RISING,FALLING]
OPTION4=CLEAR TIMER
OPTION4VALUE=[1,0]

[CONFIG-TIMER2]
SECTION=TIMERS\TIMER2
OPTIONCOUNT=4
OPTION1=TIMER2
OPTION1VALUE=[TIMER,COUNTER]
OPTION2=PRESCALE
OPTION2VALUE=[1,8,64,256,1024]
OPTION3=EDGE
OPTION3VALUE=[RISING,FALLING]
OPTION4=CLEAR TIMER
OPTION4VALUE=[1,0]

[CONFIG-TIMER3]
SECTION=TIMERS\TIMER3
OPTIONCOUNT=4
OPTION1=TIMER3
OPTION1VALUE=[TIMER,COUNTER]
OPTION2=PRESCALE
OPTION2VALUE=[1,8,64,256,1024]
OPTION3=EDGE
OPTION3VALUE=[RISING,FALLING]
OPTION4=CLEAR TIMER
OPTION4VALUE=[1,0]

[CONFIG-TIMER4]
SECTION=TIMERS\TIMER4
OPTIONCOUNT=4
OPTION1=TIMER4
OPTION1VALUE=[TIMER,COUNTER]
OPTION2=PRESCALE
OPTION2VALUE=[1,8,64,256,1024]
OPTION3=EDGE
OPTION3VALUE=[RISING,FALLING]
OPTION4=CLEAR TIMER
OPTION4VALUE=[1,0]

[CONFIG-TWI]
SECTION=I2C\TWI
OPTIONCOUNT=1
OPTION1=TWI
OPTION1VALUE=[1-400000]

[CONFIG-TWISLAVE]
SECTION=I2C\TWISLAVE
OPTIONCOUNT=6
OPTION1=TWISLAVE
OPTION1VALUE=[0,2-254]
OPTION1CODE=Dim TWI As Byte,TWI_BTR As BYTE,TWI_BTW As BYTE
OPTION2=BTR
OPTION2VALUE=[1-255]
OPTION3=BITRATE
OPTION3VALUE=[100000,400000,1-400000]
OPTION4=SAVE
OPTION4VALUE=[SAVE,NOSAVE]
OPTION5=GENCALL
OPTION5VALUE=[0,1,YES,NO]
OPTION6=USERACK
OPTION6VALUE=[OFF,ON]

[CONFIG-WAITSUART]
SECTION=WAITSUART
OPTIONCOUNT=1
OPTION1=WAITUSART
OPTION1VALUE=[1-255]

[CONFIG-WD]
SECTION=WATCHDOG
OPTIONCOUNT=1
OPTION1=WATCHDOG
OPTION1VALUE=[16,32,64,128,256,512,1024,2048,4096,8192]

[CONFIG-X10]
SECTION=X10
OPTIONCOUNT=2
OPTION1=X10
OPTION1VALUE=#PIN
OPTION2=TX
OPTION2VALUE=#PORT



[STARTLIST]
start1=TIMER0
start2=COUNTER0
start3=TIMER1
start4=COUNTER1
start5=TIMER2
start6=COUNTER2
start7=AC
start8=WATCHDOG
start9=ADC
start10=TIMER3
start11=COUNTER3


[STATEMENT1]
NAME=$Crystal
CODE=CONST _XTAL=%1

[STATEMENT2]
NAME=$version
CODE=CONST _VERSION_MAJOR=%1 : CONST _VERSION_MINOR=%2 : CONST _VERSION_BUILD=%3

[STATEMENT3]
NAME=$Resource
CODE=Dim Language as Byte

[STATEMENT4]
NAME=$Regfile
CODE=CONST _XMEGA=0

[STATEMENT5]
NAME=$SIM
CODE=CONST _SIM = 1