VHDL - Problema na compilação

[Haste]

Sou iniciante em vhdl e estou com um problema na compilação que não sei onde está o erro de sintaxe. Quem souber e puder me ajudar...

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

entity sumsub is

port (C0: in std_logic;

A0, A1, A2, A3: in std_logic;

B0, B1, B2, B3: in std_logic;

S0, S1, S2, S3: out std_logic;

C4: out std_logic);

end sumsub;

architecture rtl of sumsub is

signal P0, P1, P2, P3: std_logic;

signal G0, G1, G2, G3: std_logic;

signal C1, C2, C3: std_logic;

COMPONENT fulladder

PORT (

a, b, carryin : in std_logic;

s, carryout : out std_logic);

END COMPONENT fulladder;

begin

adder0 : fulladder PORT MAP (C0, A0, B0, S0, C1);

C_Adder: process (C0,A0,A1,A2,A3,B0,B1,B2,B3)

begin

--incompleto

end process C_Adder;

end rtl;

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

entity fulladder is

port (C0: in std_logic;

A0: in std_logic;

A1: in std_logic;

B0: out std_logic;

C1: out std_logic);

end fulladder;

architecture rtl of fulladder is

begin

Adder: process (C0,A0,A1)

begin

B0 <= C0 xor (A1 xor A0);

C1 <= (A1 and A0) or (C0 and (A1 xor A0));

end process Adder;

end rtl;

Ele da varios erros desse tipo: Can't find a pinstub/port in the symbol, function Prototyte, or other construct 'adder0' that represents a design file that corresponds to pin 'C0' in the file.

já tentei recriar o symbol fulladder, compilar pra la e pra cá...