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Rafael Pinati

PIC Comunicação Serial PIC18F4550 x PC

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Boa tarde galera, estou desenvolvendo um programa para conversar com um equipamento atraves da serial, porém estou com um problema no meu codigo, acredito que na configuração dos bits.

Desenvolvi o codigo e no simulador ele esta enviando os dados corretos, porém, quando faço o teste com um CI, não consigo enviar os dados pela serial, o software hercules (software para testes de comunicação) não o recebe.

Anexei o codigo, se puderem, me ajudem por favor.

 

PIC 18f4550, cristal de 20MHZ

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Obrigado pela dica, segue o codigo (só não consegui alterar para C, não sei porque):

main.c

#include "newfile.h"
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <plib.h>
#include <usart.h>
#include <xc.h>
#define USE_OR_MASKS
#define _XTAL_FREQ 20000000

/*
 * 
 */
//Variaveis Globais


void main()
{
    //Rotina de Iniciação
    unsigned char config = 0, spbrg=0, baudconfig = 0,i=0;
    unsigned char TxData[] = "abcdef";
    unsigned char RxData [25];
    
    configuration ();
    CloseUSART ();
    
    //configuração USART
    config = USART_TX_INT_OFF & USART_RX_INT_OFF & USART_BRGH_HIGH & USART_CONT_RX & USART_ASYNCH_MODE & USART_EIGHT_BIT & USART_ADDEN_OFF;
    spbrg = 129; //31
    baudconfig = BAUD_8_BIT_RATE & BAUD_AUTO_OFF & BAUD_WAKEUP_OFF;
    
    baudUSART(baudconfig);
    OpenUSART (config, spbrg);

    do {
        if (DataRdyUSART()){ 
            i=ReadUSART();
            WriteUSART(i);
        }
        putsUSART (TxData);
        delay(1000);
        
        }while (1);
         
} 

config.h

// CONFIG1L
  #pragma config  PLLDIV = 1            // PLL Prescaler Selection bits (No prescale (8 MHz oscillator input drives PLL directly))
  #pragma config  CPUDIV = OSC1_PLL2    // System Clock Postscaler Selection bits ([Primary Oscillator Src: /1][96 MHz PLL Src: /2])
  #pragma config  USBDIV = 1            // USB Clock Selection bit (used in Full-Speed USB mode only// UCFG:FSEN = 1) (USB clock source comes directly from the primary oscillator block with no postscale)

// CONFIG1H
  #pragma config  FOSC = HS            // Oscillator Selection bits (HS oscillator (HS))
  #pragma config  FCMEN = OFF           // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
  #pragma config  IESO = OFF            // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)

// CONFIG2L
  #pragma config  PWRT = OFF            // Power-up Timer Enable bit (PWRT disabled)
  #pragma config  BOR = ON              // Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled))
  #pragma config  BORV = 1              // Brown-out Reset Voltage bits (Minimum setting)
  #pragma config  VREGEN = OFF          // USB Voltage Regulator Enable bit (USB voltage regulator disabled)

// CONFIG2H
  #pragma config  WDT = OFF             // Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit))
  #pragma config  WDTPS = 32768         // Watchdog Timer Postscale Select bits (1:32768)

// CONFIG3H
  #pragma config  CCP2MX = OFF          // CCP2 MUX bit (CCP2 input/output is multiplexed with RB3)
  #pragma config  PBADEN = OFF           // PORTB A/D Enable bit (PORTB<4:0> pins are pragma configured as analog input channels on Reset)
  #pragma config  LPT1OSC = OFF         // Low-Power Timer 1 Oscillator Enable bit (Timer1 pragma configured for higher power operation)
  #pragma config  MCLRE = ON            // MCLR Pin Enable bit (MCLR pin enabled// RE3 input pin disabled)

// CONFIG4L
  #pragma config  STVREN = ON           // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
  #pragma config  LVP = OFF             // Single-Supply ICSP Enable bit (Single-Supply ICSP disabled)
  #pragma config  ICPRT = OFF           // Dedicated In-Circuit Debug/Programming Port (ICPORT) Enable bit (ICPORT disabled)
  #pragma config  XINST = OFF           // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))

// CONFIG5L
  #pragma config  CP0 = OFF             // Code Protection bit (Block 0 (000800-001FFFh) is not code-protected)
  #pragma config  CP1 = OFF             // Code Protection bit (Block 1 (002000-003FFFh) is not code-protected)
  #pragma config  CP2 = OFF             // Code Protection bit (Block 2 (004000-005FFFh) is not code-protected)
  #pragma config  CP3 = OFF             // Code Protection bit (Block 3 (006000-007FFFh) is not code-protected)

// CONFIG5H
  #pragma config  CPB = OFF             // Boot Block Code Protection bit (Boot block (000000-0007FFh) is not code-protected)
  #pragma config  CPD = OFF             // Data EEPROM Code Protection bit (Data EEPROM is not code-protected)

// CONFIG6L
  #pragma config  WRT0 = OFF            // Write Protection bit (Block 0 (000800-001FFFh) is not write-protected)
  #pragma config  WRT1 = OFF            // Write Protection bit (Block 1 (002000-003FFFh) is not write-protected)
  #pragma config  WRT2 = OFF            // Write Protection bit (Block 2 (004000-005FFFh) is not write-protected)
  #pragma config  WRT3 = OFF            // Write Protection bit (Block 3 (006000-007FFFh) is not write-protected)

// CONFIG6H
  #pragma config  WRTC = OFF            // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) are not write-protected)
  #pragma config  WRTB = OFF            // Boot Block Write Protection bit (Boot block (000000-0007FFh) is not write-protected)
  #pragma config  WRTD = OFF            // Data EEPROM Write Protection bit (Data EEPROM is not write-protected)

// CONFIG7L
  #pragma config  EBTR0 = OFF           // Table Read Protection bit (Block 0 (000800-001FFFh) is not protected from table reads executed in other blocks)
  #pragma config  EBTR1 = OFF           // Table Read Protection bit (Block 1 (002000-003FFFh) is not protected from table reads executed in other blocks)
  #pragma config  EBTR2 = OFF           // Table Read Protection bit (Block 2 (004000-005FFFh) is not protected from table reads executed in other blocks)
  #pragma config  EBTR3 = OFF           // Table Read Protection bit (Block 3 (006000-007FFFh) is not protected from table reads executed in other blocks)

// CONFIG7H
  #pragma config  EBTRB = OFF           // Boot Block Table Read Protection bit (Boot block (000000-0007FFh) is not protected from table reads executed in other blocks)

//configuração serial

   /* TXSTA =   0b00100100; 
    RCSTA =   0b10000000;
    BAUDCON = 0b01000000;
   
    INTCONbits.GIE = 0x00;
    INTCONbits.PEIE = 0x00;
 */
 
void delay(int c){
    for(long j = 0; j<20000*c; j++);
}
 
void configuration()
{
    
    OSCCONbits.IRCF = 0b111; //Configura oscilador interno (FOSC = 8Mhz)
    OSCCONbits.SCS = 0b10; // Fuente de Fosc del sistema = interno
    
    INTCONbits.GIE = 0x00;
    INTCONbits.PEIE = 0x00;
    //desabilita ccp
    CMCON =  0x07;
    
    TRISA = 0b00100011;                
    TRISC= 0b10111111;

    
    TXSTA =   0b00100100; 
    RCSTA =   0b10000000;
    BAUDCON = 0b01000000;
    
            
}

 

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