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For over a decade, PCI has been the standard of choice for personal computer expansion cards. PCI's bandwidth and flexibility was a stunning improvement over the old ISA and VESA Local Bus architectures of the pre-Pentium days. But, it wasn't long before the demands of the newly introduced 3D graphics revolution began to push PCI to its limits.Intel responded with the development of AGP, or Advanced Graphics Port. This advanced helped to free up the PCI bus, which was becoming overly congested with 3D graphics, and allowed for video bandwidth at rates that were 4 times faster than PCI was capable of. With the introduction of AGP, Intel single-handedly enabled the visual computing revolution.Now, 6 years after that initial launch of AGP, so much has changed. Today's AGP is in its 3rd revision, and is capable of speeds that are 16 times faster than PCI - and still, that's not enough.Today's PCI and AGP archetecture is becoming overloaded. 3D graphics are demaning ever more bandwidth, and the old PCI bus is being expected to handle more than ever before: 3D audio, gigabit networking, firewire, ATA-133, USB, and more.So, with this in mind, the industry set to developing a 3rd Generation IO format, or 3GIO. The fruit of that labor is PCI Express; and its getting ready to replace PCI and take general IO connectivity to the next level.The designers of PCI Express had a number of challenges that they had to overcome in order for PCI Express to meet all of the expectations of a next generation IO solution:· It had to be designed to support multiple market segments and application as a unifying IO architecture for Desktop, Mobile, Server, Communications, Workstations, and Embedded Devices. Quite a bit more than the original PCI desktop specification. · It had to be cheaper than PCI - in both high and low volumes. And, it had to be easier to implement. Because PCI Express is serial based rather than paralell, it requires fewer traces on PCBs, easing board design and efficiency. · It had to be compatible with the existing PCI software model, so that existing operating systems would be able to boot without any problems or changes. In addition, configuration and device drivers for PCI Express had to be compatible with exisiting PCI devices. · It had to allow for performance scalablity, which is achieved through increasing frequency and adding lanes to the bus. It was designed for a high bandwidth per pin with low overhead adn low latency, and multiple virtual channels per physical link are supported. · It had to be a point-to-point connection, which allows each device ot have its own dedicated connection without having to share a bus. In addition to these features, a number of other advanced features were incorporated:· The ability to work with different types of data structures. · Low power consumption and power management features. · Quality of service policies. · Hot swappability and hot pluggability for devices. · Data integrity and error handling end-to-end and at the link level. · Isochronous data transfer support. · Host based transfers through host bridge chips and peer-to-peer transfers through switches. · Packetized and layered protol architecture. In implementation, PCI Express is based on a root complex that can be placed in either the North or South bridge of the motherboard, switches, and end-point devices. The new feature that PCI Express brings with it here are the switches. Much like network switches, these replace teh old multi-drop bus and provide true peer-to-peer data communication between all of the different end-point devices. More importantly, it does not require traffic to be forwarded to the host bridge (except in cases that involve cache-coherent memory transfers).The most basic PCI Express link is made up of two signals: a transmit and a receive. The data clock is embedded directly into the signal using a 8/10 bit encoding scheme that allows for very high data rates. The initial speeds are expected to be about 2.5 Gigabits per second in each direction, with speeds expected to increase to as high as 10 Gigabits per second as the technology develops.One of the more important improvements is PCI Express's ability to scale speeds by aggregating links to form multiple lanes. This means that you can make a PCI Express connector faster simply by increasing its length (essentially adding more connections). This is all done with comeplete transparency to the other layers - so no special support is required. In this manner, PCI Express can support speeds of 1x, 2x, 4x, 8x, 12x, 16x, and 32x. Graphics adapters based on PCI Express technology will be using the 16x mode - meaning that you will get troughput of about 40.0 Gigabits per second in each direction (that's about 4 Gigabytes per second at peak) - as compared to the ~2.128 Gigabytes per second that we see now from 8X AGP. With even more performance as the technology develops.So, what does the future hold for computers using PCI Express? Well, first off, the PCI that we know and love so well will not die right away (the same cannot be said for AGP however). Next generation motherboards will likely support both PCI and PCI Express side by side by means of an additional header placed at the end of a standard PCI slot to support lower bandwidth (1 and 2 lane) PCI Express devices; somewhat similar to the extra connector used for 66 MHz PCI devices. This, combined with the full software support will allows for a seamless integration with older PCI technology.Moving farther into the future, we will see PCI Express based technology replace PC cards in notebooks, and begin to make the idea of a modular computer a real possibility.The big names in the computer industry like Intel, NVIDIA, Microsoft, and AMD have already thrown their support behind PCI Express. With supporters like that, it seems to be a pretty sure thing that the PCI Express I/O system will be the new standard for many years to come.

:ahh:

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Postado Originalmente por condiogo@10 jul 2004, 15:00

starfox-jp

For over a decade, PCI has been the standard of choice for personal computer expansion cards. PCI's bandwidth and flexibility was a stunning improvement over the old ISA and VESA Local Bus architectures of the pre-Pentium days. But, it wasn't long before the demands of the newly introduced 3D graphics revolution began to push PCI to its limits.Intel responded with the development of AGP, or Advanced Graphics Port. This advanced helped to free up the PCI bus, which was becoming overly congested with 3D graphics, and allowed for video bandwidth at rates that were 4 times faster than PCI was capable of. With the introduction of AGP, Intel single-handedly enabled the visual computing revolution.Now, 6 years after that initial launch of AGP, so much has changed. Today's AGP is in its 3rd revision, and is capable of speeds that are 16 times faster than PCI - and still, that's not enough.Today's PCI and AGP archetecture is becoming overloaded. 3D graphics are demaning ever more bandwidth, and the old PCI bus is being expected to handle more than ever before: 3D audio, gigabit networking, firewire, ATA-133, USB, and more.So, with this in mind, the industry set to developing a 3rd Generation IO format, or 3GIO. The fruit of that labor is PCI Express; and its getting ready to replace PCI and take general IO connectivity to the next level.The designers of PCI Express had a number of challenges that they had to overcome in order for PCI Express to meet all of the expectations of a next generation IO solution:· It had to be designed to support multiple market segments and application as a unifying IO architecture for Desktop, Mobile, Server, Communications, Workstations, and Embedded Devices. Quite a bit more than the original PCI desktop specification. · It had to be cheaper than PCI - in both high and low volumes. And, it had to be easier to implement. Because PCI Express is serial based rather than paralell, it requires fewer traces on PCBs, easing board design and efficiency. · It had to be compatible with the existing PCI software model, so that existing operating systems would be able to boot without any problems or changes. In addition, configuration and device drivers for PCI Express had to be compatible with exisiting PCI devices. · It had to allow for performance scalablity, which is achieved through increasing frequency and adding lanes to the bus. It was designed for a high bandwidth per pin with low overhead adn low latency, and multiple virtual channels per physical link are supported. · It had to be a point-to-point connection, which allows each device ot have its own dedicated connection without having to share a bus. In addition to these features, a number of other advanced features were incorporated:· The ability to work with different types of data structures. · Low power consumption and power management features. · Quality of service policies. · Hot swappability and hot pluggability for devices. · Data integrity and error handling end-to-end and at the link level. · Isochronous data transfer support. · Host based transfers through host bridge chips and peer-to-peer transfers through switches. · Packetized and layered protol architecture. In implementation, PCI Express is based on a root complex that can be placed in either the North or South bridge of the motherboard, switches, and end-point devices. The new feature that PCI Express brings with it here are the switches. Much like network switches, these replace teh old multi-drop bus and provide true peer-to-peer data communication between all of the different end-point devices. More importantly, it does not require traffic to be forwarded to the host bridge (except in cases that involve cache-coherent memory transfers).The most basic PCI Express link is made up of two signals: a transmit and a receive. The data clock is embedded directly into the signal using a 8/10 bit encoding scheme that allows for very high data rates. The initial speeds are expected to be about 2.5 Gigabits per second in each direction, with speeds expected to increase to as high as 10 Gigabits per second as the technology develops.One of the more important improvements is PCI Express's ability to scale speeds by aggregating links to form multiple lanes. This means that you can make a PCI Express connector faster simply by increasing its length (essentially adding more connections). This is all done with comeplete transparency to the other layers - so no special support is required. In this manner, PCI Express can support speeds of 1x, 2x, 4x, 8x, 12x, 16x, and 32x. Graphics adapters based on PCI Express technology will be using the 16x mode - meaning that you will get troughput of about 40.0 Gigabits per second in each direction (that's about 4 Gigabytes per second at peak) - as compared to the ~2.128 Gigabytes per second that we see now from 8X AGP. With even more performance as the technology develops.So, what does the future hold for computers using PCI Express? Well, first off, the PCI that we know and love so well will not die right away (the same cannot be said for AGP however). Next generation motherboards will likely support both PCI and PCI Express side by side by means of an additional header placed at the end of a standard PCI slot to support lower bandwidth (1 and 2 lane) PCI Express devices; somewhat similar to the extra connector used for 66 MHz PCI devices. This, combined with the full software support will allows for a seamless integration with older PCI technology.Moving farther into the future, we will see PCI Express based technology replace PC cards in notebooks, and begin to make the idea of a modular computer a real possibility.The big names in the computer industry like Intel, NVIDIA, Microsoft, and AMD have already thrown their support behind PCI Express. With supporters like that, it seems to be a pretty sure thing that the PCI Express I/O system will be the new standard for many years to come.

:ahh:

pois é... ahauhahuauhahuauhauha se bem que eu sei lê em inglês mas tem gente q não :/

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