Outro VHDL somar unsigned com std_logic

[Aoi Todo]

Oi, estou tentando fazer um programa que conta quantos 1's tem um std_logic_vector. Mas nao consigo fazer o codigo funcionar. Aparece o erro:

Line 27. unsigned can not have such operands with returned type UNSIGNED.

Meu código é o seguinte:

 

--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use IEEE.NUMERIC_STD.ALL;

entity proj2_1 is
	 GENERIC (N: INTEGER := 8); -- TAMANHO DO VETIN 
    Port ( VTIN : in  STD_LOGIC_VECTOR (7 downto 0);
           VTOUT : out  STD_LOGIC_VECTOR (7 downto 0);
			  cont: buffer unsigned  (7 downto 0) );
end proj2_1;




architecture Behavioral of proj2_1 is



begin
	gen: FOR i IN VTIN' RANGE GENERATE	
	BEGIN

		cont <= cont + ( unsigned (VTIN(i)));
	END GENERATE;
    VTOUT <= std_logic_vector(cont);

end Behavioral;